|
|
A/D Converter. ADC10DL065 Datasheet |
|
|
|
June 2006
ADC10DL065
Dual 10-Bit, 65 MSPS, 3.3V, 370mW A/D Converter
www.datashGeete4un.ceomral Description
The ADC10DL065 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 10-bit digital words at 65 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption
while providing excellent dynamic performance and a 250
MHz Full Power Bandwidth. Operating on a single +3.3V
power supply, the ADC10DL065 achieves 9.8 effective bits
at nyquist and consumes just 370 mW at 65 MSPS, including
the reference current. The Power Down feature reduces
power consumption to 36 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times VREF with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADC’s are available on a single multiplexed 10-bit
bus or on separate buses. Duty cycle stabilization and output
data format are selectable using a quad state function pin.
The output data can be set for offset binary or two’s comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC10DL065 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage. This device is available in the
64-lead TQFP package and will operate over the industrial
temperature range of −40˚C to +85˚C. An evaluation board is
available to ease the evaluation process.
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Internal reference
n Outputs 2.4V to 3.6V compatible
n Power down mode
n Duty Cycle Stabilizer
n Multiplexed Output Mode
Key Specifications
n Resolution
n DNL
n SNR (fIN = 10 MHz)
n SFDR (fIN = 10 MHz)
n Data Latency
n Power Consumption
n -- Operating
n -- Power Down Mode
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n DSP Front Ends
10 Bits
±0.16 LSB (typ)
61 dB (typ)
85 dB (typ)
7 Clock Cycles
370 mW (typ)
36 mW (typ)
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation DS201486
20148601
www.national.com
|
Ordering Information
Industrial (−40˚C ≤ TA ≤ +85˚C)
ADC10DL065CIVS
ADC10DL065EVAL
Block Diagram
www.datasheet4u.com
Package
64 Pin TQFP
Evaluation Board
www.national.com
20148602
2
|
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
Symbol
15 VINA+
2 VINB+
www.datasheet4u.com
16
1
VINA−
VINB−
Equivalent Circuit
Description
Differential analog input pins. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 VP-P with each
input pin voltage centered on a common mode voltage, VCM.
The negative input pins may be connected to VCM for
single-ended operation, but a differential input signal is
required for best performance.
7 VREF
21 DF/DCS
This pin is the reference select pin and the external reference
input.
If (VA - 0.3V) < VREF < VA, the internal 1.0V reference is
selected.
If AGND < VREF < (AGND + 0.3V), the internal 0.5V reference
is selected.
If a voltage in the range of 0.8V to 1.2V is applied to this pin,
that voltage is used as the reference. VREF should be
bypassed to AGND with a 0.1 µF capacitor when an external
reference is used.
This is a four-state pin.
DF/DCS = VA, output data format is offset binary with duty
cycle stabilization applied to the input clock
DF/DCS = AGND, output data format is 2’s complement, with
duty cycle stabilization applied to the input clock.
DF/DCS = VRMA or VRMB , output data is 2’s complement
without duty cycle stabilization applied to the input clock
DF/DCS = "float", output data is offset binary without duty cycle
stabilization applied to the input clock.
13 VRPA
5 VRPB
14 VRMA
4 VRMB
12
6
DIGITAL I/O
60
VRNA
VRNB
CLK
22 OEA
41 OEB
These pins are high impedance reference bypass pins. All
these pins should each be bypassed to ground with a 0.1 µF
capacitor. A 10 µF capacitor should be placed between the
VRPA and VRNA pins and between the VRPB and VRNB pins.
VRMA and VRMB may be loaded to 1mA for use as a
temperature stable 1.5V reference. The remaining pins should
not be loaded.
Digital clock input. The range of frequencies for this input is as
specified in the electrical tables with guaranteed performance
at 65 MHz. The input is sampled on the rising edge.
OEA and OEB are the output enable pins that, when low, holds
their respective data output pins in the active state. When
either of these pins is high, the corresponding outputs are in a
high impedance state.
3 www.national.com
|
| @ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |