A/D Converter. ADC10DV200 Datasheet

ADC10DV200 Converter. Datasheet pdf. Equivalent

ADC10DV200 Datasheet
Recommendation ADC10DV200 Datasheet
Part ADC10DV200
Description 200 MSPS Low-Power A/D Converter
Feature ADC10DV200; ADC10DV200 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel Outputs February 5, 2009 AD.
Manufacture National Semiconductor Corporation
Datasheet
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National Semiconductor Corporation ADC10DV200
ADC10DV200
February 5, 2009
Dual 10-bit, 200 MSPS Low-Power A/D Converter with
Parallel LVDS/CMOS Outputs
www.daGtasehneeet4ru.acolmDescription
The ADC10DV200 is a monolithic analog-to-digital converter
capable of converting two analog input signals into 10-bit dig-
ital words at rates up to 200 Mega Samples Per Second
(MSPS). The digital output mode is selectable and can be ei-
ther differential LVDS or CMOS signals. This converter uses
a differential, pipelined architecture with digital error correc-
tion and an on-chip sample-and-hold circuit to minimize die
size and power consumption while providing excellent dy-
namic performance. A unique sample-and-hold stage yields
a full-power bandwidth of 900MHz. Fabricated in core CMOS
process, the ADC10DV200 may be operated from a single
1.8V power supply. The ADC10DV200 achieves approxi-
mately 9.6 effective bits at Nyquist and consumes just 280mW
at 170MSPS in CMOS mode and 450mW at 200MSPS in
LVDS mode. The power consumption can be scaled down
further by reducing sampling rates.
Applications
Communications
Medical Imaging
Portable Instrumentation
Digital Video
Features
Single 1.8V power supply operation.
Power scaling with clock frequency.
Internal sample-and-hold.
Internal or external reference.
Power down mode.
Offset binary or 2's complement output data format.
LVDS or CMOS output signals.
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
Clock Duty Cycle Stabilizer.
IF Sampling Bandwidth > 900MHz.
Key Specifications
Resolution
Conversion Rate
ENOB
SNR
SINAD
SFDR
LVDS Power
CMOS Power
Operating Temp. Range
10 Bits
200 MSPS
9.6 bits (typ) @Fin=70MHz
59.9 dBFS (typ) @Fin=70MHz
59.9 dBFS (typ) @Fin=70MHz
82 dBFS (typ) @Fin=70MHz
450mW (typ) @Fs=200MSPS
280mW (typ) @Fs=170MSPS
−40°C to +85°C.
Block Diagram
© 2009 National Semiconductor Corporation 300820
30082002
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National Semiconductor Corporation ADC10DV200
Connection Diagram
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Ordering Information
Industrial (−40°C TA +85°C)
ADC10DV200CISQ
ADC10DV200CISQE
ADC10DV200EB
Package
60 Pin LLP
60 Pin LLP,
250 pc. Tape and Reel
Evaluation Board
30082001
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National Semiconductor Corporation ADC10DV200
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
13
3
Symbol
VINA+
VINB+
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14
VINA-
2 VINB-
Equivalent Circuit
Description
Differential analog input pins. The differential full-scale input
signal level is 1.5VP-P with each input pin signal centered on
a common mode voltage, VCM.
10 VRPA
6 VRPB
11 VRMA
5 VRMB
9 VRNA
7 VRNB
17 VREF
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very
close to the pin to minimize stray inductance. An 0201 size 0.1
µF capacitor should be placed between VRP and VRN as close
to the pins as possible.
VRP and VRN should not be loaded. VRM may be loaded to 1mA
for use as a temperature stable 0.9V reference.
It is recommended to use VRM to provide the common mode
voltage, VCM for the differential analog inputs.
Reference Voltage select pin and external reference input.
The relationship between the voltage on the pin and the
reference voltage is as follows:
1.4V VREF VA
The internal 0.75V reference is
used.
0.2V VREF 1.4V
The external reference voltage is
used.
Note: When using an external
reference, be sure to bypass with
a 0.1µF capacitor to AGND as
close to the pin as possible.
AGND VREF 0.2V
The internal 0.5V reference is
used.
19 REXT
Programming resistor for analog bias current. Nominally a
3.3kto AGND for 200MSPS, or tie to VA to use the internal
frequency scaling current.
20 DF/DCS
Data Format/Duty Cycle Correction selection pin.
(see Table 1)
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