Ferquency Synthesizers. AN95102 Datasheet

AN95102 Synthesizers. Datasheet pdf. Equivalent

AN95102 Datasheet
Recommendation AN95102 Datasheet
Part AN95102
Description Low Power Single/Dual Ferquency Synthesizers
Feature AN95102; Philips Semiconductors Application note Low power single/dual frequency synthesizers: UMA1017M/101.
Manufacture Philips
Download AN95102 Datasheet

Philips AN95102
Philips Semiconductors
Low power single/dual frequency synthesizers:
Application note
Author: P. Hugues
UMA1018M and UMA1020M/UMA1020AM low power dual frequency synthesizers
UMA1017M and UMA1019M/UMA1019AM low power single frequency synthesizers
This application note describes the UMA1018M and
UMA1020M/UMA1020AM from Philips Semiconductors. They
permit a low-voltage low-power single-chip solution to designing
dual PLL frequency synthesizers. They are intended for use in
digital or analogue wireless communications equipment. Typical
applications include GSM, DECT and DCS1800.
Three low-voltage low-power solutions to single frequency
synthesizers are also briefly described. The UMA1017M and
UMA1019M/UMA1019AM are derivatives from UMA1018M and
UMA1020M, respectively, and are hence closely related.
The overall performance of any PLL frequency synthesizer system
is critically determined by the low pass filter used. Described in this
report is a basic loop filter design method with worked examples and
some measurement results.
1.1 General description
The UMA1018M [1] is a low power low voltage single chip solution
to a dual frequency synthesizer used in radiocommunications.
Designed in a BICMOS process, it operates from 2.7 (3 NiCd cells)
to 5.5 V. The UMA1018M contains all the necessary elements with
the exception of the VTCXO, VCO and loop filters to build two PLL
frequency synthesizers.
It is intended that the principal synthesizer operates in the 50 to
1250 MHz range, and the auxiliary synthesizer will work between 20
and 300 MHz. For each synthesizer, fully programmable main and
reference dividers are integrated on chip. The reference input
FXTAL can operate from 5 to 40 MHz. Fast programming is
possible via the three wire serial bus with clock speeds of up to 10
The principal synthesizer phase detector drives a low current charge
pump and a high current charge pump simultaneously. Maximum
output current is 0.4 mA with the low current charge pump (pin CPP)
and 3.2 mA with the other (pin CPPF). The auxiliary phase detector
drives only one charge pump. The programmable charge pump
currents are fixed by an external resistance Rext at pin lSET. Only
passive loop filters are necessary.
To reduce crosstalk between different parts of the synthesizer,
separate power supply and ground pins are provided to the
analogue and digital sections.
Each synthesizer can be powered down independently to save
current via software programming or hardwire pins AON / PON.
An on-chip 7 bit DAC allows adjustment of external functions, such
as temperature compensation of the VTCXO, power amplifier
control, etc.
Dual frequency synthesizers
Operating voltage range 2.7 to 5.5 V for battery powered
Low current consumption, 10 mA typically at 5.5 V (two PLLs
Integrated fully programmable main divider for each synthesizer
Principal: 512 to 131,071 up to 1.25 GHz input
Auxiliary: 64 to 16,383 up to 300 MHz input
Independent fully programmable reference divider for each
Principal: 8 to 2074 up to 2 MHz output
Auxiliary: 8 to 2047 up to 1 MHz output
3-wire serial bus (Data, Clock, Enable) for fast programming
(fmax = 10 MHz)
Independent hardwire and software power down modes for both
Simple passive loop filters
Charge pump output current under bus control, with reference
current ISET set by an external reference resistor Rext
Programmable out-of-lock detector
Integrated D-to-A converter
Small SSOP-20 package
1995 Oct 10
906 Revision of AN94002

Philips AN95102
Philips Semiconductors
Low power single/dual frequency synthesizers:
Application note
Figure 1–1. UMA1018M Block Diagram
1.3 Typical Application Architecture
UMA1018M integrated circuit is typically used in digital
radiotelephone systems like GSM. It is designed to meet the
requirements of these systems; low noise (residual and spurious),
fast switching and low current consumption (at 5.5 V: 10 mA with
both synthesizers ON and 36 µA with both synthesizers OFF).
Figure 1–1 demonstrates a typical application. UMA1018M is
integrated on a dual superheterodyne architecture using two local
1995 Oct 10
Figure 1–2. UMA1018M: Typical Application Block Diagram

Philips AN95102
Philips Semiconductors
Low power single/dual frequency synthesizers:
Application note
1.4 UMA1018M Family
To satisfy the need of the emerging digital communication systems,
a family of synthesizer controls based around the UMA1018M has
been developed.
1.4.1 UwMwwA.1d0a2ta0sMh/eUeMt4Au1.c0o2m0AM Dual Synthesizers
UMA1020M [2] is used in 2 GHz applications, like PHP, DCS1800 or
DECT. Its principal synthesizer operates from 1.7 to 2.4 GHz. It
offers the same functions as the UMA1018M dual synthesizer
including the 7-bit DAC. The UMA1020AM [3] principal synthesizer
works from 1 to 1.7 GHz. It does not include the DAC.
1.4.2 UMA1017M and UMA1019M/UMA1019AM Single
The UMA1017M [4] and UMA1019M/UMA1019AM integrated
circuits are derivatives from UMA1018M and UMA1020M,
respectively with similar pinning. They contain the principal
synthesizer only. UMA1017M operates from 50 to 1250 MHz,
UMA1019M [5] from 1.7 to 2.4 GHz and UMA1019AM [6] from 1 to
1.7 GHz. Neither contains the auxiliary synthesizer or the DAC (see
Figure 1–3).
In this application note, no extra mention will be made about
UMA1020AM and the single synthesizers. All UMA1018M and
UMA1020M principal synthesizer descriptions and results are valid
for other circuits.
Table, overleaf, summarizes characteristics and typical applications
of each synthesizer.
Figure 1–3. UMA1017M and UMA1019M/UMA1019AM Block Diagram
Table 1–1. Frequency Synthesizers Update
Part No.
2.7 to 5.5 V
7.7 mA (5.5 V)
36 µA (PD)
2.7 to 5.5 V
2.7 to 5.5 V
2.7 to 5.5 V
2.7 to 5.5 V
10 mA (5.5 V)
36 µA (PD)
9.4 mA (5.5 V)
36 µA (PD)
9.4 mA (5.5 V)
36 µA (PD)
12.1 mA (5.5 V)
36 µA (PD)
2.7 to 5.5 V
12.1 mA (5.5 V)
36 µA (PD)
RF Input Frequency
50 to 1250 MHz
50 to 1250 MHz (main)
20 to 300 MHz (aux)
1 to 1.7 GHz
1.7 to 2.4 GHz
1 to 1.7 GHz (main)
20 to 300 MHz (aux)
1.7 to 2.4 GHz (main)
20 to 300 MHz (aux)
Main Applications
CT2 digital cordless
GSM digital cellular
General purpose
Cellular systems like GSM Applications with
UHF and VHF synthesizers
General purpose
Cordless and wireless radios
General purpose
Ideal for DECT superhet
Digital cordless and wireless radios
The principle of the Phase Locked Loop (PLL) is illustrated in the
PLL application block diagram (Figure 3–1).
A crystal (VTCXO) provides a reference frequency to the PLL. A
phase detector drives a charge pump to send correction current
pulses to a low pass filter. Current pulses are proportional to the
difference in phase between the two phase detector input signals.
The filter integrates the pulses giving a voltage which controls a
Voltage Controlled Oscillator. VCO frequency and crystal frequency
are divided down to a common comparison frequency to control the
phase detector. The PLL is locked when the phase difference
between input signals is maintained null.
1995 Oct 10

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