Document
ICS664-01
Digital Video Clock Source
Description
The ICS664-01 provides clock generation and conversion for clock rates commonly needed in HDTV www.datasheet4u.com digital video equipment. The ICS664-01 uses the latest PLL technology to provide excellent phase noise and long term jitter performance for superior synchronization and S/N ratio. For audio sampling clocks generated from 27 MHz, use the ICS661. Please contact ICS if you have a requirement for an input and output frequency not included in this document. ICS can rapidly modify this product to meet special requirements.
Features
• • • • • • •
Packaged in 16-pin TSSOP Clock or crystal input provides flexibility Low phase noise supports enhanced SNR Lowest jitter in class at 100 ps Exact (0 ppm) multiplication ratios Power-down mode lowers power consumption Improved phase noise over ICS660
Block Diagram
VDD (P2) VDD (P3) VDDO VDD (P14)
X2 Crystal Oscillator
X1/REFIN
SELIN S3:0
4
PLL Clock Synthesis
CLK
GND (P13)
GND (P6)
GND (P5)
MDS 664-01 A Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 050704 tel (408) 297-1201
●
www.icst.com
ICS664-01 Digital Video Clock Source
Pin Assignment
X1/REFIN
www.datasheet4u.com VDD
Output Clock Selection Table
16 15 14 13 12 11 10 9 X2 N/C VDD GND SELIN VDDO S1 CLK
1 2 3 4 5 6 7 8
S3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
S0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Input Frequency (MHz)
Pass thru 27 27 13.5 13.5 RESERVED RESERVED 74.25 74.175824 RESERVED RESERVED 54 54 54 27
Output Frequency (MHz)
Power down Input Freq 74.25 74.175824 74.25 74.175824 RESERVED RESERVED 54
VDD S0 GND GND S3 S2
54
RESERVED RESERVED 74.25 74.175824 13.5 13.5
16-pin TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X1/REFIN VDD VDD S0 GND GND S3 S2 CLK S1 VDDO SEL GND VDD NC X2
Pin Type
Input Power Power Input Power Power Input Input Output Input Power Input Power Power — Input Power supply for crystal oscillator. Power supply for PLL.
Pin Description
Connect this pin to a crystal or clock input
Output frequency selection. Determines output frequency per table above. On chip pull up. Ground for output stage. Ground for PLL. Output frequency selection. Determines output frequency per table above. On chip pull up. Output frequency selection. Determines output frequency per table above. On chip pull up. Clock output. Output frequency selection. Determines output frequency per table above. On chip pull up. Power supply for output stage. Low for clock input, high for crystal. On chip pull up. Connect to ground. Power supply. No connect. Do not connect to anything. Connect this pin to a crystal. Leave open if using a clock input.
MDS 664-01 A
2
●
Revision 050704 tel (408) 297-1201
●
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-01 Digital Video Clock Source
Application Information
Series Termination Resistor
Clock output traces should use series termination. To series terminate a 50Ω trace (a commonly used trace www.datasheet4u.com impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. adjust the stray capacitance of the board to match the nominally required crystal load capacitance. To reduce possible noise pickup, use very short PCB traces (and no vias) been the crystal and device. The value of the load capacitors can be roughly determined by the formula C = 2(CL - 6) where C is the load capacitor connected to X1 and X2, and CL is the specified value of the load capacitance for the crystal. A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF. Because these capacitors adjust the stray capacitance of the PCB, check the output frequency using your final layout to see if the value of C should be changed.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS664-01 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS664-01 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less crit.