Clock Source. ICS664-04 Datasheet

ICS664-04 Source. Datasheet pdf. Equivalent

ICS664-04 Datasheet
Recommendation ICS664-04 Datasheet
Part ICS664-04
Description PECL Digital Video Clock Source
Feature ICS664-04; ICS664-04 PECL Digital Video Clock Source Description The ICS664-04 provides clock generation and co.
Manufacture Integrated Circuit Systems
Datasheet
Download ICS664-04 Datasheet




Integrated Circuit Systems ICS664-04
ICS664-04
PECL Digital Video Clock Source
Description
The ICS664-04 provides clock generation and
www.dactaosnhveeetr4sui.oconmfor clock rates commonly needed in HDTV
digital video equipment. The ICS664-04 uses the latest
Phase-Locked Loop (PLL) technology to provide
excellent phase noise and long-term jitter performance
for superior synchronization and S/N ratio.
For audio sampling clocks generated from 27 MHz, use
the ICS661.
Please contact ICS if you have a requirement for an
input and output frequency not included in this
document. ICS can rapidly modify this product to meet
special requirements.
Features
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Clock or crystal input
Low phase noise
Low jitter
Exact (0 ppm) multiplication ratios
Power-down control
Improved phase noise over ICS660
Differential outputs
Block Diagram
X2
X1/REFIN
SELIN
S3:0 4
VDD (P2)
Crystal
Oscillator
GND (P6)
VDD (P3) VDDO
VDD (P10)
PLL Clock
Synthesis
GND (P5)
CLK
CLK
GND (P12)
MDS 664-04 A
1
Revision 040805
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com



Integrated Circuit Systems ICS664-04
ICS664-04
PECL Digital Video Clock Source
Pin Assignment
X1/REFIN
www.datasheet4u.coVmDD
VDD
S0
GND
GND
S3
S2
1
2
3
4
5
6
7
8
16 X2
15 VDDO
14 CLK
13 CLK
12 GND
11 SELIN
10 VDD
9 S1
16-pin 4.40 mil body, 0.65 mm pitch TSSOP
Pin Descriptions
Output Clock Selection Table
Input
Output
S3 S2 S1 S0 Frequency Frequency
(MHz)
(MHz)
0000
Power down
0001
Pass thru
Input Freq
0010
27
74.25
0 0 1 1 27 74.175824
0100
13.5
74.25
0 1 0 1 13.5 74.175824
0110
27
148.5
0111
27 148.351648
1000
74.25
54
1 0 0 1 74.175824
54
1010
74.25
27
1 0 1 1 74.175824
27
1100
54
74.25
1 1 0 1 54 74.175824
1110
54
13.5
1111
27
13.5
Pin Pin
Number Name
1 X1/REFIN
2 VDD
3 VDD
4 S0
5 GND
6 GND
7 S3
8 S2
9 S1
10 VDD
11 SELIN
12 GND
13 CLK
14 CLK
15 VDDO
16 X2
Pin
Type
Pin Description
Input Connect this pin to a crystal or clock input
Power Power supply for crystal oscillator.
Power Power supply for PLL.
Input Output frequency selection. Determines output frequency per table above. On chip pull-up.
Power Ground for PLL.
Power Ground for oscillator.
Input Output frequency selection. Determines output frequency per table above. On chip pull-up.
Input Output frequency selection. Determines output frequency per table above. On chip pull-up.
Input Output frequency selection. Determines output frequency per table above. On chip pull-up.
Power Power supply.
Input Low for clock input, high for crystal. On chip pull-up.
Power Ground for output stage
Output Complimentary clock output.
Output Clock output.
Power Power supply for output stage.
Input Connect this pin to a crystal. Leave open if using a clock input.
MDS 664-04 A
2
Revision 040805
Integrated Circuit Systems, Inc.525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com



Integrated Circuit Systems ICS664-04
ICS664-04
PECL Digital Video Clock Source
Application Information
Termination Resistor
Terminate the outputs with 50to ground.
www.datasheet4u.com
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS664-04 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS664-04 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
Recommended Power Supply Connection for
Optimal Device Performance
Connection to 3.3V
Power Plane
Ferrite
Bead
VDD Pin
VDD Pin
Bulk Decoupling Capacitor
(such as 1 F Tantalum)
VDD Pin
0.01 F Decoupling Capacitors
All power supply pins must be connected to the same
voltage, except VDDO, which may be connected to a
lower voltage in order to change the output level.
To achieve the absolute minimum jitter, power the part
with a dedicated LDO regulator, which will provide high
isolation from power supply noise. Many companies
produce very small, inexpensive regulators; an
example is the National Semiconductor LP2985.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(CL - 6) where C is the
load capacitor connected to X1 and X2, and CL is the
specified value of the load capacitance for the crystal.
A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI, and obtain the best signal integrity,
the 50series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS664-04. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
MDS 664-04 A
3
Revision 040805
Integrated Circuit Systems, Inc.525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com





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