ICS664-04

ICS664-04 PECL Digital Video Clock Source Description The ICS664-04 provides clock generation and conversion for clock rates commonly needed in HDTV www.datasheet4u.com digital video equipment. The ICS664-04 uses the latest Phase-Locked Loop (PLL) technology to provide excellent phase noise and long-term jitter performance for superior synchronization and S/N ratio. For audio sampling clocks generated from 27 MHz, use the ICS661. Please contact ICS if you have a requirement for an input and output frequency not included in this document. ICS can rapidly modify this product to meet special requirements. Features Packaged in 16-pin TSSOP Available in Pb (lead) free package Clock or crystal input Low phase noise Low jitter Exact (0 ppm) multiplication ratios Power-down control Improved phase noise over ICS660 Differential outputs Block Diagram VDD (P2) VDD (P3) VDDO VDD (P10) X2 Crystal Oscillator X1/REFIN SELIN S3:0 4 PLL Clock Synthesis CLK CLK GND (P6) GND (P5) GND (P12) MDS 664-04 A Integrated Circuit Systems, Inc. ● 1 525 Race Street, San Jose, CA 95126 ● Revision 040805 tel (408) 297-1201 ● www.icst.com ICS664-04 PECL Digital Video Clock Source Pin Assignment X1/REFIN www.datasheet4u.com Output Clock Selection Table 16 15 14 13 12 11 10 9 X2 VDDO CLK CLK GND SELIN VDD S1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pass thru 27 27 13.5 13.5 27 27 74.25 74.1...