Management Controller. ADJD-J823 Datasheet

ADJD-J823 Controller. Datasheet pdf. Equivalent

ADJD-J823 Datasheet
Recommendation ADJD-J823 Datasheet
Part ADJD-J823
Description Color Management Controller
Feature ADJD-J823; www.DataSheet4U.com ADJD-J823 Color Management Controller with Integrated RGB Photosensor Data Sh.
Manufacture AVAGO TECHNOLOGIES LIMITED
Datasheet
Download ADJD-J823 Datasheet





AVAGO TECHNOLOGIES LIMITED ADJD-J823
www.DataSheet4U.com
ADJD-J823
Color Management Controller with Integrated RGB Photosensor
Data Sheet
Description
The ADJD-J823 is a CMOS mixed-signal IC with integrated
RGB photosensors designed to be the optical feedback
device of an RGB LED-based backlighting system. A
typical system consists of an array of red, green and blue
(RGB) LEDs, LED drivers and the ADJD-J823. The device
samples the light output from the RGB LED array, pro-
cesses the color information and adjusts the light output
from the RGB LEDs until the target color is achieved. To
achieve this, the device integrates an RGB photosensor
array, an analog-to-digital converter front-end, a color
data processing logic core and a high-resolution 12-bit
PWM output generator.
By employing a feedback system and the ADJD-J823,
the light output produced by the LED array maintains
its color over time and temperature. In addition, using
a serial interface, specifying the color of the LED array’s
light output is as simple as picking the target color co-
ordinates from the CIE color space and writing several
bytes of data to the device.
The sensitivity of the device to light can be adjusted
through an automated process. The PWM output signals
control the on-time duration of the red, green and blue
LEDs. That duration is continually adjusted in real-time
to match the light output from the RGB LED array to the
target color.
Features
Integrated RGB photosensor
Integrated color management feedback controller
Serial Interface
Direct interface to standard I2C EEPROM
3-channel 12-bit PWM output –
Red, Green and Blue LED channels
Built-in oscillator
Applications
LCD Backlighting
ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge.
AVAGO TECHNOLOGIES’ PRODUCTS AND SOFTWARE ARE NOT SPECIFICALLY DESIGNED, MANUFACTURED OR AUTHORIZED FOR SALE AS
PARTS, COMPONENTS OR ASSEMBLIES FOR THE PLANNING, CONSTRUCTION, MAINTENANCE OR DIRECT OPERATION OF A NUCLEAR FACILITY
OR FOR USE IN MEDICAL DEVICES OR APPLICATIONS. CUSTOMER IS SOLELY RESPONSIBLE, AND WAIVES ALL RIGHTS TO MAKE CLAIMS
AGAINST AVAGO TECHNOLOGIES OR ITS SUPPLIERS, FOR ALL LOSS, DAMAGE, EXPENSE OR LIABILITY IN CONNECTION WITH SUCH USE.



AVAGO TECHNOLOGIES LIMITED ADJD-J823
www.DataSheet4U.com
Package Dimensions
A
Seating Plane
0.65 ref
1.05
5.0 ± 0.1
0.75 ± 0.1
0.2 ref
0.3
3.2 ref
3.2 ref
5.0 ± 0.1
Note: Dimensions are in millimeter (mm)
Bottom View
Pin 15
Pin 14
Pin 13
Pin 12
Pin 11
Pin 1
marker
notch
Pin 1
0.5 ref




AVAGO TECHNOLOGIES LIMITED ADJD-J823
www.DataSheet4U.com
Pin Information
PIN NAME
1 NC
2 PWMB
3 PWMG
4 PWMR
5 DGND
6 DGND
7 DVDD
8 AGND
9 CLKIO
10 XRST
TYPE
No connect
Output
Output
Output
Ground
Ground
Power
Ground
Output
Input
11 SCLSLV
12 SDASLV
Input
Input/Output
(tri-state high)
13 SCLPROM Output
14 SDAPROM Input/Output
(tri-state high)
15 SLEEP
Input
16 AGND
17 AGND
18 AGND
19 AVDD
20 NC
Ground
Ground
Ground
Power
No connect
DESCRIPTION
No connect. Leave floating.
PWMB is the active-high blue pulse width modulation output pin.
Tie it to the blue LED driver channel.
PWMG is the active-high green pulse width modulation output pin.
Tie it to the green LED driver channel.
PWMR is the active-high red pulse width modulation output pin.
Tie it to the red LED driver channel.
Tie to digital ground.
Tie to digital ground.
Digital power pin.
Tie to analog ground.
CLKIO outputs a reference internal clock signal.
Global, asynchronous, active low system reset.
When asserted low, XRST resets all registers.
Minimum reset pulse low is 10us and must be provided by external
circuitry.
SDASLV and SCLSLV are the serial interface communications pins.
SDASLV is the bidirectional data pin and SCLSLV is the interface clock.
A pull-up resistor should be tied to SDASLV because it goes tri-state to
output logic 1.
An external serial I2C EEPROM can be connected to the device to store
calibration and configuration data. SDAPROM and SCLPROM should be
tied to the I2C data (SDA) and clock (SCL) pins of the EEPROM. A pull-up
resistor should be tied to SDAPROM because it goes tri-state to output
logic 1.
When SLEEP=1, the device goes into sleep mode. In sleep mode, all
analog circuits are powered down and the clock signal is gated away from
the core logic resulting in very low current consumption.
Tie to analog ground.
Tie to analog ground.
Tie to analog ground.
Analog power pin.
No connect. Leave floating.






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