Document
NJW1184
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4-CHANNEL ELECTRONIC VOLUME
s GENERAL DESCRIPTION The NJW1184 is a four channel electronic volume. The NJW1184 performs click-noiseless characteristics with VCA circuit. These functions are controlled by I2C Bus. And the Slave Address selector is available for using two chips on same serial bus line. It’s available for two-channel stereo and or multi-channel audio volume. s PACKAGE OUTLINE
NJW1184M
NJW1184D
s FEATURES q Operating Voltage 2 q I C Bus control q Slave Address Selector q Volume (VCA type) q 2 Auxiliary Port q Bi-CMOS Technology q Package Outline
7.5 to 13V available for using two chips on same serial bus line 0 to –100dB/0.5dBstep, MUTE DMP20, DIP20
s BLOCK DIAGRAM
IN1
OUT1
IN3
OUT3 CVOL1 CVOL2 CVOL3 CVOL4
I C Bus Interface
2
VOL1
VOL3
AUX0 AUX1 ADR SCL
VOL2
VOL4 Bias
SDA V+ GND
IN2
OUT2
IN4
OUT4
Vref
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NJW1184
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sPIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10
IN1 OUT1 IN2 OUT2 CVOL1 CVOL2 ADR SDA SCL GND
IN3 OUT3 IN4 OUT4 CVOL3 CVOL4 AUX1 AUX0 Vref V+
20 19 18 17 16 15 14 13 12 11
No.
1 2 3 4 5 6 7 8 9 10
Symbol
IN1 OUT1 IN2 OUT2 CVOL1 CVOL2 ADR SDA SCL GND Input 1 Output 1 Input 2 Output 2
Function
No
11 12 13 14 15 16 17 18 19 20
Symbol
V+ Vref AUX0 AUX1 CVOL4 CVOL3 OUT4 IN4 OUT3 IN3
Function
Power Supply Pin Reference Voltage Auxiliary Output0 Auxiliary Output1 DAC Output for Volume 4 DAC Output for Volume 3 Output 4 Input 4 Output 3 Input 3
DAC Output for Volume 1 DAC Output for Volume 2 Slave Address Setting SDA Data Input (I2C BUS) SCL Data Input (I2C BUS) GND
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NJW1184
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s ABSOLUTE MAXIMUM RATING (Ta=25°C)
PARAMETER Supply Voltage Maximum Input Voltage Power Dissipation Operating Temperature Range Storage Temperature Range SYMBOL V
+
RATING 15 0 to V DIP20 : 700
+(✴)
UNIT V V mW °C °C
VIM PD Topr Tstg
DMP20 : 350
-40 to +85 -40 to +125
(✴) For the maximum input voltage less than 0 toV+
s ELECTRICAL CHARACTERISTICS
(Ta=25°C, V+=9V, RL=47kΩ, Vin=100mVrms/1kHz, unless otherwise specified) qPOWER SUPPLY PARAMETER Operating Voltage Supply Current Reference Voltage qVOLUME PARAMETER Maximum Input Voltage Maximum Output Voltage Channel Balance Total Harmonic Distortion Maximum Gain Minimum Gain Channel Separation Output Noise 1 Output Noise 2 Input Impedance AUX Output Voltage SYMBOL VIM VOM GCB THD GVMAX GVMIN CS VNO1 VNO2 Ri VAUX Logic Output: High Logic Output: Low qCONTROL PARAMETER SYMBOL VADRH VADRL TEST CONDITION
High : Slave Address 82H Low : Slave Address 80H
SYMBOL V
+
TEST CONDITION
MIN. 7.5
TYP. 9.0 4 4.5
MAX. 13.0 10 5.0
UNIT V mA V
ICC VREF
No Signal No Signal
4.0
TEST CONDITION VOL=-20dB,THD=1% OUTPUT VOL=0dB,THD=1% VOL=0dB Vo=0.5Vrms BW=400Hz to 30kHz VOL= 0dB VOL= MUTE, Vin=2Vrms Vin = 1Vrms A-weighting VOL = 0dB A-weighting VOL = MUTE A-weighting
MIN. 2.8 -1.0 -2.0 4.5 0
TYP. 3.0 2.5 0.0 0.0 -100 -80 -90 (31.6) -106 (5.0) 20 -
MAX. 1.0 0.3 2.0 -90 -70 -85 (56.2) -96 (15.8) 5.5 0.5
UNIT Vrms Vrms dB % dB dB dB dBV (µVrms) dBV (µVrms) kΩ
V
BW: Band Width
MIN. V /2 +
TYP. -
MAX. 1.0
UNIT
High Level Input Voltage Low Level Input Voltage
V V
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NJW1184
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s I C BUS CHARACTERISTICS
2
2
(SDA, SCL) SYMBOL
VIL VIH Vhys VOL tof tSP Ii Ci fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF Cb VnL
I C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
Low Level Input Voltage High Level Input Voltage Hysteresis of Schmitt trigger inputs Low level output voltage (3mA at SDA pin) Output fall time from VIHmin to VILmax with a bus capacitance from 10pF to 400pF Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax Capacitance for each I/O pin SCL clock frequency Hold time (repeated) START condition. Low period of the SCL clock High period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the Low level Noise margin at the High level
Standard mode
MIN. 0.0 2.7 0 -10 4.0 4.7 4.0 4.7 0 250 4.0 4.7 0.5 1 TYP. MAX. 1.5 5.0 0.4 250 10 10 100 3.45 1000 300 400 MIN. 0.0 2.7 0.25 0
Fast mode
TYP. MAX. 1.5 5.0 0.4 250 50 10 10 400 0.9 300 300 400 -
UNIT
V V V V ns ns µA pF kHz µs µs µs µs µs ns ns ns µs µs pF V
20 +0.1Cb
0 -10 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0.5 1
VnH
V
Cb ; total capacitance of one bus line in pF.
SDA
tf
tr
tSU:DAT
tf
tHD:STA
tSP
tr
tBUF
SCL
tHD:STA S tLOW tHD:DAT tHIGH
tSU:STA Sr
tSU:STO P S
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NJW1184
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! TERMINAL DESCRIPTION
PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE
V+
1 3 20 18
IN1 IN2 IN3 IN4
Input 1 Input 2 Input 3 Input 4
20k Ω
V /2
+
V+
2 4 19 17
OUT1 .