Plerow APL0335
www.DataSheet4U.com
PLL Module Description
The plerowTM PLL synthesizer module was designed for use in wireless and wireline systems in a wide range of frequency from 50 MHz to 6 GHz. ASB’s PLL provides exceptionally low spurious and phase noise performance with fast locking time and low current consumption. All products are available in a surface-mount type package.
Features
∙ +3 dBm Output Level at 335 MHz ∙ Channel Step Size : 100 kHz ∙ 2
nd
Harmonic : < - 20dBc
∙ Spurious Level : < -70dBc ∙ Lock Time : < 10 ms ∙ 30 mA Current Consumption ∙ Strip-line Resonator
Specifications
Parameter Frequency Range Output Power Supply Voltage Current Consumption Channel Step Size 2 Harmonics Spurious Level Lock Time Reference Frequency Reference Input Level Phase Noise (C / N) @ 1 kHz @ 10 kHz @ 100 kHz Output Impedance Operating Temp. Range Package Type & Size Ω °C mm -40 dBc/Hz -80 -105 -120 50 25 SMT, 19.0W×19.0L×5.8H 85 -75 -102 -115
nd
Unit MHz dBm V mA kHz dBc dBc us MHz dBm
Min. 330 1
Typical 335 3 5 23 100 -25 -75 3 10
Max. 340 5
More Information
Website: www.asb.co.kr E-mail:
[email protected] Tel: (82) 42-528-7220 Fax: (82) 42-528-7222 ASB Inc., 4th Fl. Venture Town Bldg., 367-17 Goijeong-Dong, Seo-Gu, Daejon 302-716, Korea
30
-20 -70 10
-4
0
5
1) Measurement conditions are as follows: T = 25°C, VCC = 5.0 V, Freq. = 335 MHz, 50 ohm system.
Outline Drawing
Top View Bottom View
Pin Configuration Dimension (mm) A 19.0 B 19.0 C 5.8 D 1.5 E 0.5 F 1.75 G 1.35 H 15.0 I 0.9 Tolerance: ± 0.2
D A E F I C B Side View
1/1 www.asb.co.kr
H
G
1 2 3 4 9 13 15 16 Others
CLOCK DATA ENABLE OSC IN VCC (VCO) RF OUT VCP (PLL) LOCK DETECT Ground
December 2004
.