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LF2242 Dataheets PDF



Part Number LF2242
Manufacturers LOGIC Devices Incorporated
Logo LOGIC Devices Incorporated
Description 12/16-bit Half-Band Interpolating/ Decimating Digital Filter
Datasheet LF2242 DatasheetLF2242 Datasheet (PDF)

LF2242 DEVICES INCORPORATED DEVICES INCORPORATED 12/16-bit Half-Band Interpolating/ Decimating Digital Filter DESCRIPTION The LF2242 is a linear-phase, halfband (low pass) interpolating/ decimating digital filter that, unlike intricate analog filters, requires no tuning. The LF2242 can also significantly reduce the complexity of traditional analog anti-aliasing prefilters without compromising the signal bandwidth or attenuation. This can be achieved by using the LF2242 as a decimating post-fil.

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LF2242 DEVICES INCORPORATED DEVICES INCORPORATED 12/16-bit Half-Band Interpolating/ Decimating Digital Filter DESCRIPTION The LF2242 is a linear-phase, halfband (low pass) interpolating/ decimating digital filter that, unlike intricate analog filters, requires no tuning. The LF2242 can also significantly reduce the complexity of traditional analog anti-aliasing prefilters without compromising the signal bandwidth or attenuation. This can be achieved by using the LF2242 as a decimating post-filter with an A/D converter and by sampling the signal at twice the rate needed. Likewise, by using the LF2242 as an interpolating pre-filter with a D/A converter, the corresponding analog reconstruction post-filter circuitry can be simplified. The coefficients of the LF2242 are fixed, and the only user programming required is the selection of the mode (interpolate, decimate, or passthrough) and rounding. The asynchronous three-state output enable control simplifies interfacing to a bus. Data can be input into the LF2242 at a rate of up to 40 million samples per second. Within the 40 MHz I/O limit, the output sample rate can be onehalf, equal to, or two times the input 12/16-bit Half-Band Interpolating/ Decimating Digital Filter LF2242 FEATURES u 40 MHz Clock Rate u Passband (0 to 0.22fS) Ripple: ±0.02 dB u Stopband (0.28fS to 0.5fS) Rejection: 59.4 dB u User-Selectable 2:1 Decimation or 1:2 Interpolation u 12-bit Two’s Complement Input and 16-bit Output with User-Selectable Rounding, 8- to 16-Bits u User-Selectable Two’s Complement or Inverted Offset Binary Output Formats u Three-State Outputs u Replaces TRW/ Raytheon/ Fairchild TMC2242 u Package Styles Available: • 44-pin PLCC, J-Lead • 44-pin PQFP sample rate. Once data is clocked in, the 55-value output response begins after 7 clock cycles and ends after 61 clock cycles. The pipeline latency from the input of an impulse response to its corresponding output peak is 34 clock cycles. The output data may be in either two’s complement format or inverted offset binary format. To avoid truncation errors, the output data is always internally rounded before it is latched into the output register. Rounding is user-selectable, and the output data can be rounded from 16 bit values down to 8 bit values. DC gain of the LF2242 is 1.0015 (0.0126 dB) in pass-through and decimate modes and 0.5007 (–3.004 dB) in interpolate mode. Passband ripple does not exceed ±0.02 dB from 0 to 0.22fS with stopband attenuation greater than 59.4 dB from 0.28fS to 0.5fS (Nyquist frequency). The response of the filter is –6 dB at 0.25fS. Full compliance with CCIR Recommendation 601 (–12 dB at 0.25fS) can be achieved by cascading two devices serially. LF2242 BLOCK DIAGRAM TCO RND2–0 3 3 55-TAP FIR FILTER ROUND AND LIMIT CIRCUIT SI11–0 12 INTERPOLATION 12 CIRCUIT 16 DECIMATION CIRCUIT 16 SO15–0 3 3 CLK TO ALL REGISTERS OE INT DEC SYNC Video Imaging Products 1 08/16/2000–LDS.2242-K LF2242 DEVICES INCORPORATED 12/16-bit Half-Band Interpolating/ Decimating Digital Filter Controls INT — Interpolation Control When INT is LOW and DEC is HIGH (Table 1), the device internally forces every other incoming data sample to zero. This effectively halves the input data rate and the output amplitude. DEC — Decimation Control When DEC is LOW and INT is HIGH (Table 1), the output register is strobed on every other rising edge of CLK (driven at half the clock rate), decimating the output data stream. FIGURE 1. FREQUENCY RESPONSE OF FILTER 0 –10 –20 GAIN (dB) –30 –40 –50 –60 –70 –80 0 0.1ƒS 0.2ƒS 0.3ƒS 0.4ƒS 0.5ƒS FREQUENCY (NORMALIZED) TABLE 1. INT 0 DEC 0 1 0 1 MODE SELECTION MODE Pass-through* Interpolate Decimate Pass-through* SIGNAL DEFINITIONS Power VCC and GND Inputs SI11–0 — Data Input 0 1 1 12-bit two’s complement data input port. Data is latched into the register on +5 V power supply. All pins must be the rising edge of CLK. The LSB is SI0 (Figure 2). connected. *Input and output registers run at full clock rate Clock CLK — Master Clock Outputs SO15-0 Data Output The rising edge of CLK strobes all regis- The current 16-bit result is available on ters. All timing specifications are refer- the SO15-0 outputs. The LF2242’s limiter ensures that a valid full-scale (7FFF enced to the rising edge of CLK. positive or 8000 negative) output will be generated in the event of an internal SYNC — Synchronization Control overflow. The LSB is SO0 (Figure 2). Incoming data is synchronized by holding SYNC HIGH on CLKN, and then by bringing SYNC LOW on CLKN+1 with the first word of input data. SYNC is held LOW until resynchronization is desired, or it can be toggled at half the clock rate. For interpolation (INT = LOW), input data should be presented at the first rising edge of CLK for which SYNC is LOW and then at every alternate rising edge of CLK thereafter. SYNC is inactive if DEC and INT are equal (pass-through mode). Video Imaging Products 2 08/16/2000–LDS.2242-K LF2242 DEVICES INCORPOR.


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