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STD78N75F4 STP78N75F4
N-channel 75 V, 0.008 Ω, 78 A TO-220, DPAK STripFET™ DeepGATE™ Power MOSFET
Preliminary data
Features
Type STD78N75F4 STP78N75F4
■ ■ ■ ■
VDSS 75 V 75 V
RDS(on) max < 0.011 Ω < 0.011 Ω
ID 70 A 78 A
3 1
N-channel enhancement mode 100% avalanched rated Low gate charge Very low on-resistance
3 1 2
DPAK
TO-220
Application
■
Switching applications
Figure 1.
Internal schematic diagram
Description
This STripFET™ DeepGATE™ Power MOSFET technology is among the latest improvements, which have been especially tailored to minimize on-state Resistance, with a new gate structure, providing superior switching performances.
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Table 1.
Device summary
Marking 78N75F4 78N75F4 Package DPAK TO-220 Packaging Tape and reel Tube
Order codes STD78N75F4 STP78N75F4
May 2009
Doc ID 15682 Rev 1
1/12
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Contents
STD78N75F4, STP78N75F4
Contents
1 2 3 4 5 6 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuit ................................................ 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STD78N75F4, STP78N75F4
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID ID IDM
(1)
Absolute maximum ratings
Value Parameter TO-220 Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C Derating factor 78 55 312 150 1 TBD – 55 to 175 Operating junction temperature 75 ± 20 70 50 280 125 0.83 DPAK V V A A A W W/°C mJ °C Unit
PTOT
(2)
EAS
Single pulse avalanche energy Storage temperature
Tstg Tj
1. Pulse width limited by safe operating area 2. Starting Tj = 25 °C, ID= 32.5 A, VDD= 45 V
Table 3.
Symbol Rthj-case Rthj-a Rthj-pcb Tl
(1)
Thermal data
Value Parameter TO-220 Thermal resistance junction-case max Thermal resistance junction-ambient max Thermal resistance junction-pcb max Maximum lead temperature for soldering purpose 300 1 62.5 50 DPAK 1.2 °C/W °C/W °C/W °C Unit
1. When mounted on FR-4 board of 1 inch², 2 oz Cu
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Electrical characteristics
STD78N75F4, STP78N75F4
2
Electrical characteristics
(TCASE = 25 °C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source Breakdown voltage Zero gate voltage Drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 µA, VGS = 0 VDS = max rating VDS = max rating,TC=125 °C VGS = ± 20 V VDS = VGS, ID = 250 µA VGS = 10 V, ID = 37.5 A 2 0.008 Min. 75 1 100 100 4 0.011 Typ. Max. Unit V µA µA nA V Ω
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge VDS = 25 V, f = 1 MHz, VGS = 0 Test conditions Min. Typ. 5130 415 20 VDD = 60 V, ID = 78A, VGS = 10 V (see Figure 3) 90 TBD TBD Max. Unit pF pF pF nC nC nC
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 50 V, ID = 37.5 A RG = 4.7 Ω VGS = 10 V (see Figure 2) VDD = 50 V, ID = 37.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 2) Min. Typ. TBD TBD TBD TBD Max. Unit ns ns ns ns
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STD78N75F4, STP78N75F4 Table 7.
Symbol ISD ISDM (1) VSD
(2)
Electrical characteristics
Source drain diode
Parameter Source-drain current DPAK TO-220 Source-drain current (pulsed) DPAK Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 78 A, VGS = 0 ISD = 78 A, VDD = 25 V di/dt = 100 A/µs, Tj = 150 °C (see Figure 4) TBD TBD TBD 280 1.5 A V ns nC A 70 312 A A Test conditions TO-220 Min. Typ. Max 78 Unit A
trr Qrr IRRM
-
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
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Test circuit
STD78N75F4, STP78N75F4
3
Figure 2.
Test circuit
Switching times test circuit for resistive load Figure 3. Gate charge test circuit
VDD 12V
2200
47kΩ 100nF
1kΩ
RL VGS VD RG PW D.U.T.
µF
3.3 µF
VDD Vi=20V=VGMAX
2200 µF
IG=CONST 2.7kΩ 47kΩ PW 1kΩ
100Ω
D.U.T. VG
AM01468v1
AM01469v1
Figure 4.
Test circui.