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PTN3360B Dataheets PDF



Part Number PTN3360B
Manufacturers NXP
Logo NXP
Description Enhanced Performance HDMI/DVI Level Shifter
Datasheet PTN3360B DatasheetPTN3360B Datasheet (PDF)

www.DataSheet4U.com PTN3360B Enhanced performance HDMI/DVI level shifter Rev. 01 — 4 May 2009 Product data sheet 1. General description The PTN3360B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals, up to 2.5 Gbit/s per lane. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled different.

  PTN3360B   PTN3360B


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www.DataSheet4U.com PTN3360B Enhanced performance HDMI/DVI level shifter Rev. 01 — 4 May 2009 Product data sheet 1. General description The PTN3360B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals, up to 2.5 Gbit/s per lane. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the PTN3360B provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel for level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using pass-gate technology providing level shifting as well as disablement (isolation between source and sink) of the clock and data lines. The low-swing AC-coupled differential input signals to the PTN3360B typically come from a display source with multi-mode I/O, which supports multiple display standards, e.g., DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.3a specification. By using PTN3360B, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1. The PTN3360B main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications.The I2C-bus channel level-translates the DDC signals between 3.3 V (source) and 5.0 V (sink). The PTN3360B is a fully featured HDMI as well as DVI level shifter. It is functionally equivalent to PTN3300A but provides higher speed performance and higher ESD robustness. The PTN3360B is also equivalent to PTN3360A with the exception that PTN3360B provides non-inverting level shifting on the HPD channel. PTN3360B is powered from a single 3.3 V power supply consuming a small amount of power (120 mW typ.) and is offered in a 48-terminal HVQFN48 package. www.DataSheet4U.com NXP Semiconductors PTN3360B Enhanced HDMI/DVI level shifter MULTI-MODE DISPLAY SOURCE OE_N reconfigurable I/Os PCIe PHY ELECTRICAL TMDS coded data PCIe output buffer TX FF TX TMDS coded data PCIe output buffer TX FF TX TMDS coded data PCIe output buffer TX FF TX TMDS clock pattern PCIe output buffer TX FF TX AC-coupled differential pair clock CLOCK LANE OUT_D1+ OUT_D1− IN_D1+ IN_D1− AC-coupled differential pair TMDS data DATA LANE IN_D2+ IN_D2− OUT_D2+ OUT_D2− AC-coupled differential pair TMDS data IN_D3+ DATA LANE IN_D3− OUT_D3+ OUT_D3− AC-coupled differential pair TMDS data IN_D4+ DATA LANE IN_D4− OUT_D4+ OUT_D4− PTN3360B 0 V to 3.3 V HPD_SOURCE_N HPD_SINK 0 V to 5 V 3.3 V 3.3 V DDC_EN (0 V to 3.3 V) 5V SCL_SOURCE 3.3 V DDC I/O (I2C-bus) CONFIGURATION SDA_SOURCE SCL_SINK 5V SDA_SINK 002aae267 Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1]. Fig 1. Typical application system diagram PTN3360B_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 4 May 2009 DVI CONNECTOR 2 of 21 www.DataSheet4U.com NXP Semiconductors PTN3360B Enhanced HDMI/DVI level shifter 2. Features 2.1 High-speed TMDS level shifting I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals I TMDS level shifting operation up to 2.5 Gbit/s per lane (250 MHz character clock) I Integrated 50 Ω termination resistors for self-biasing differential inputs I Back-current safe outputs to disallow current when device power is off and monitor is on I Disable feature to turn off TMDS inputs and outputs and to enter low-power state 2.2 DDC level shifting I Integrated DDC level shifting (3.3 V source to 5 V sink side) I 0 Hz to 400 kHz I2C-bus clock frequency I Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled 2.3 HPD level shifting I HPD non-inverting level shift from 5 V on the sink side to 3.3 V on the source side, or from 0 V on the sink side to 0 V on the source side I Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when no display is plugged in I Back-power safe design on HPD_SINK to disallow backdrive current when power is off 2.4 General I I I I I Power supply 3.3 V ± 10 %.


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