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DS34S104 Dataheets PDF



Part Number DS34S104
Manufacturers Maxim Integrated Products
Logo Maxim Integrated Products
Description (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip
Datasheet DS34S104 DatasheetDS34S104 Datasheet (PDF)

ABRIDGED DATA SHEET www.DataSheet4U.com Rev: 101708 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up.

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ABRIDGED DATA SHEET www.DataSheet4U.com Rev: 101708 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standardsbased TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. The high level of integration available with the DS34S10x devices minimizes cost, board space, and time to market. ♦ ♦ ♦ ♦ ♦ ♦ Features Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments 64 Independent Bundles/Connections Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet VLAN Support According to 802.1p and 802.1Q 10/100 Ethernet MAC Supports MII/RMII/SSMII Selectable 32-Bit, 16-Bit or SPI Processor Bus Operates from Only Two Clock Signals, One for Clock Recovery and One for Packet Processing Glueless SDRAM Buffer Management Low-Power 1.8V Core, 3.3V I/O Applications TDM Circuit Extension Over PSN o Leased-Line Services Over PSN o TDM Over GPON/EPON o TDM Over Cable o TDM Over Wireless Cellular Backhaul Over PSN Multiservice Over Unified PSN HDLC-Based Traffic Transport Over PSN ♦ ♦ ♦ ♦ ♦ ♦ ♦ See detailed feature list in Section 5 . Functional Diagram CPU Bus Ordering Information PART DS34S101GN * DS34S101GN+* DS34S102GN* DS34S102GN+* DS34S104GN DS34S104GN+ DS34S108GN DS34S108GN+ PORTS TEMP RANGE 1 1 2 2 4 4 8 8 -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 256 TECSBGA 256 TECSBGA 256 TECSBGA 256 TECSBGA 256 TECSBGA 256 TECSBGA 484 HSBGA 484 HSBGA DS34S108 TDM Interfaces Circuit Emulation Engine 10/100 Ethernet MAC xMII Interface Manager Buffer Clock Adapters SDRAM Interface Clock Inputs +Denotes lead-free/RoHS-compliant package (explanation). *Future product—contact factory for availability. ________________________________________________________ Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. ABRIDGED DATA SHEET www.DataSheet4U.com ____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 1 Applicable Standards Table 1-1. Applicable Standards SPECIFICATION IEEE IEEE 802.3 IEEE 1149.1 IETF RFC 4553 RFC 4618 RFC 5086 RFC 5087 ITU-T G.823 G.824 G.8261/Y.1361 I.363.1 I.363.2 I.366.2 O.151 O.161 Y.1413 Y.1414 Y.1452 Y.1453 MEF MEF 8 MFA MFA 4.0 MFA 5.0.0 MFA 8.0.0 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications (2005) Standard Test Access Port and Boundary-Scan Architecture, 1990 Structure-Agnostic Time Division Multiplexing (TDM) over Packet (SAToP) (06/2006) Encapsulation Methods for Transport of PPP/High-Level Data Link Control (HDLC) over MPLS Networks (09/2006) Structure-Aware Time Division Multiplexed (TDM) Circuit Emulation Service over Packet Switched Network (CESoPSN) (12/2007) Time Division Multiplexing over IP (TDMoIP) (12/2007) The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps Hierarchy (03/2000) The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps Hierarchy (03/2000) Timing and Synchronization Aspects in Packet Networks (05/2006) B-ISDN ATM Adaptation Layer Specification: Type 1 AAL (08/1996) B-ISDN ATM Adaptation Layer Specification: Type 2 AAL (11/2000) AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services (11/2000) Error Performance Measuring Equipment Operating at the Primary Rate and Above (1992) In-Service Code Violation Monitors for Digital Systems (1993) TDM-MPLS Network Interworking – User Plane Interworking (03/2004) Voice Services–MPLS Network Interworking (07/2004) Voice Trunking over IP Networks (03/2006) TDM-IP Interworking – User Plane Networking (03/2006) Implementation Agre.


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