HDMI Retimer. DS34RT5110 Datasheet
May 11, 2009
DVI, HDMI Retimer with Input Equalization and Output De-
The DS34RT5110 is a 10.2 Gbps (3 x 3.4 Gbps) high perfor-
mance re-clocking device that supports 3 Transition Mini-
mized Differential Signaling (TMDS®) data channels and a
single clock channel over DVI™ v1.0, and HDMI™ v1.3a data
rates up to 3.4 Gbps for each data channel. The device in-
corporates a configurable receive equalizer, a clock and data
recovery (CDR) circuit and a de-emphasis driver on each data
channel. The clock channel feeds a high-performance phase-
locked loop (PLL) that regenerates a low jitter output clock for
The DS34RT5110 equalizes and retimes greater than 25 me-
ters 28 AWG of HDMI cable for 1080p resolution with 12 bit
deep color depth (2.25 Gbps), to a low jitter version of the
clock and data signal outputs, reducing both deterministic and
random jitter. Several devices can be cascaded for long links
without degrading signal fidelity. Obtaining total jitter is 0.09
UI or less over the supported data rates. This low level of out-
put jitter provides system designers with extra margin and
flexibility when working with stringent timing budgets.
The transmitter supports configurable transmit de-emphasis
so the output can be optimized for driving additional lengths
of cables or FR4 traces.
■ Optimized for HDMI/DVI repeater applications
■ TMDS compatible inputs with configurable receive
equalization supporting data rates up to 3.4 Gbps
■ TMDS compatible outputs with configurable transmit de-
■ Dedicated CDR on each data channel reduces jitter
transfer, enabling multiple devices to be cascaded without
impairing signal fidelity
■ Capable of multi-hop extension of HDMI/DVI applications
at data rates between 250 Mbps and 3.4 Gbps
■ Resistor adjustable differential output voltage for AC
coupled Cat5e and Cat6 extension applications
■ 2 equalizer settings for a wide range of cable reaches at
different data rates
■ Total Output Jitter of 0.09 UI at 2.25 Gbps
■ Total Output Jitter of 0.10 UI at 3.4 Gbps
■ DVI 1.0 and HDMI v1.3a compatible TMDS source and
■ 7 mm x 7 mm 48 pin LLP package
■ >8 kV HBM ESD protection
■ 0 °C to +70 °C operating temperature
■ Repeater Applications
— Digital Routers
— HDMI / DVI Extender Multi-hops
■ Source Applications
— Video Cards
— Blu-ray DVD Players
— Game Consoles
■ Sink Applications
— High Definition Displays
© 2009 National Semiconductor Corporation 300873
Pin Name Pin Number I/O, Type
High Speed Differential I/O
1 I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50 Ω terminating
2 resistor connects C_IN+ to VDD and C_IN- to VDD.
4 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
5 resistor connects D_IN0+ to VDD and D_IN0- to VDD.
8 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
9 resistor connects D_IN1+ to VDD and D_IN1- to VDD.
11 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
12 resistor connects D_IN2+ to VDD and D_IN2- to VDD.
36 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT0− 33 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT1– 29 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT2− 26 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
37 I, LVCMOS EQ2, EQ1 and EQ0 select the equalizer boost level for EQ channels. Internally pulled LOW
38 as default. See Table 1.
42 I, DE1, DE0 select the DE-emphasis level for output drivers. Internally pulled low as default.
43 LVCMOS Refer to Table 2.
47 I, Reclocker enable control. Internally pulled low as default.
LVCMOS H = Reclock and De-Emphasis function is bypassed.
L = Normal operation.
EN 44 I, LVCMOS Enable Output Drivers. Internally pulled HIGH as default.
H = normal operation (enabled).
L = standby mode.
21 I, LVCMOS Clock channel mode control. Internally pulled LOW as default.
H = Clock channel is bypassed.
L = Normal operation.
SD 45 O, LVCMOS Signal Detect Output pin.
H = signal detected on all channels.
L = no signal detected on one or more channels.
14 O, LVCMOS Lock Indicator Output pin.
H = PLL is locked.
L = PLL is not locked.
VOD control pin. Refer to Table 3. See Functional Description.
External resistance = 24 kΩ to GND, Output DC Coupled Application.
External resistance = 12 kΩ to GND, Output AC Coupled Application.
LFp 40 I, Loop filter capacitor pins.
LFn 41 Analog See Functional Description.