MOSFET Driver. ADP3120A Datasheet

ADP3120A Driver. Datasheet pdf. Equivalent

Part ADP3120A
Description 12V MOSFET Driver
Feature ADP3120A Dual Bootstrapped, 12 V MOSFET Driver with Output Disable The ADP3120A is a single Phase 1.
Manufacture ON Semiconductor
Datasheet
Download ADP3120A Datasheet



ADP3120A
ADP3120A
Dual Bootstrapped, 12 V
MOSFET Driver with Output
Disable
The ADP3120A is a single Phase 12 V MOSFET gate drivers
optimized to drive the gates of both highside and lowside power
MOSFETs in a synchronous buck converter. The highside and
lowside driver is capable of driving a 3000 pF load with a 45 ns
propagation delay and a 25 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 35 V, with transient voltages as high as 40 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
Features
AllInOne Synchronous Buck Driver
Bootstrapped HighSide Drive
One PWM Signal Generates Both Drives
Anticross Conduction Protection Circuitry
OD for Disabling the Driver Outputs Meets CPU VR Requirement
when Used with Patented FlexModet Controller
These are PbFree Devices
Applications
Multiphase Desktop CPU Supplies
SingleSupply Synchronous Buck Converters
© Semiconductor Components Industries, LLC, 2012
June, 2012 Rev. 4
1
8
1
1
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SO8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
3120A
ALYW
G
1
DFN8
MN SUFFIX
CASE 506BJ
18
L3C
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
PIN CONNECTIONS
BST 1
IN
OD
VCC
8 DRVH
SWN
PGND
DRVL
18
BST DRVH
IN SWN
OD PGND
VCC DRVL
(Top View)
ORDERING INFORMATION
Device
Package Shipping
ADP3120AJRZ
SO8
98 Units / Rail
(PbFree)
ADP3120AJRZRL SO8 2500 Tape & Reel
(PbFree)
ADP3120AJCPZRL DFN8 5000 Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
ADP3120A/D



ADP3120A
OD 3
IN 2
VCC
TSD
UVLO
START STOP
MIN DRVL
OFF TIMER
ADP3120A
FALLING
EDGE
DELAY
FALLING
EDGE
DELAY
NONOVERLAP
TIMERS
MONITOR
MONITOR
Figure 1. Block Diagram
1 BST
8 DRVH
7 SWN
4 VCC
5 DRVL
6 PGND
PIN DESCRIPTION
SO8 DFN8 Symbol
1 1 BST
2 2 IN
3 3 OD
4 4 VCC
5 5 DRVL
6 6 PGND
7 7 SWN
8 8 DRVH
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the highside MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 mF. An external diode is required with the ADP3120A.
LogicLevel Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
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