MOSFET Driver. ADP3120A Datasheet
Dual Bootstrapped, 12 V
MOSFET Driver with Output
The ADP3120A is a single Phase 12 V MOSFET gate drivers
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 45 ns
propagation delay and a 25 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 35 V, with transient voltages as high as 40 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
• All−In−One Synchronous Buck Driver
• Bootstrapped High−Side Drive
• One PWM Signal Generates Both Drives
• Anticross Conduction Protection Circuitry
• OD for Disabling the Driver Outputs Meets CPU VR Requirement
when Used with Patented FlexModet Controller
• These are Pb−Free Devices
• Multiphase Desktop CPU Supplies
• Single−Supply Synchronous Buck Converters
© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 4
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
98 Units / Rail
ADP3120AJRZ−RL SO−8 2500 Tape & Reel
ADP3120AJCPZ−RL DFN8 5000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Publication Order Number:
Figure 1. Block Diagram
SO−8 DFN8 Symbol
1 1 BST
2 2 IN
3 3 OD
4 4 VCC
5 5 DRVL
6 6 PGND
7 7 SWN
8 8 DRVH
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 mF. An external diode is required with the ADP3120A.
Logic−Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.