MOSFET Driver. ADP3121 Datasheet
Dual Bootstrapped, 12 V
MOSFET Driver with Output
The ADP3121 is a dual, high voltage MOSFET driver optimized for
driving two N−channel MOSFETs, the two switches in a non−isolated
synchronous buck power converter. Each driver is capable of driving a
3000 pF load with a 20 ns propagation delay and a 15 ns transition
One of the drivers can be bootstrapped and is designed to handle the
high voltage slew rate associated with floating high−side gate drivers.
The ADP3121 includes overlapping drive protection to prevent
shoot−through current in the external MOSFETs.
The OD pin shuts off both the high−side and the low−side
MOSFETs to prevent rapid output capacitor discharge during system
The ADP3121 is specified over the commercial temperature range
of 0°C to 85°C and is available in 8−lead SOIC_N and 8−lead LFCSP
• All−In−One Synchronous Buck Driver
• Bootstrapped High−Side Drive
• One PWM Signal Generates Both Drives
• Anticross Conduction Protection Circuitry
• Overvoltage Protection
• OD for Disabling the Driver Outputs
• Meets CPU VR Requirement when Used with Flex−Modet
• These are Pb−Free Devices
• Multiphase Desktop CPU Supplies
• Single Supply Synchronous Buck Converters
P3121A = Device Code
AL = Assembly Location
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
L7Q = Device Code
# = Pb−Free Package
Y = Year
WW = Work Week
ADP3121JRZ−RL SOIC_N 2500/Tape & Reel
ADP3121JCPZ−RL LFCSP_VD 5000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
© Semiconductor Components Industries, LLC, 2010
February, 2010 − Rev. 1
Publication Order Number:
Figure 1. Block Diagram
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds
this bootstrapped voltage for the high−side MOSFET while it is switching.
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this
pin low turns on the low−side driver; pulling it high turns on the high−side driver.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with an ~1 mF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched
voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.