MOSFET Driver. ADP3121 Datasheet

ADP3121 Driver. Datasheet pdf. Equivalent

Part ADP3121
Description 12V MOSFET Driver
Feature .
Manufacture ON Semiconductor
Datasheet
Download ADP3121 Datasheet



ADP3121
ADP3121
Dual Bootstrapped, 12 V
MOSFET Driver with Output
Disable
The ADP3121 is a dual, high voltage MOSFET driver optimized for
driving two Nchannel MOSFETs, the two switches in a nonisolated
synchronous buck power converter. Each driver is capable of driving a
3000 pF load with a 20 ns propagation delay and a 15 ns transition
time.
One of the drivers can be bootstrapped and is designed to handle the
high voltage slew rate associated with floating highside gate drivers.
The ADP3121 includes overlapping drive protection to prevent
shootthrough current in the external MOSFETs.
The OD pin shuts off both the highside and the lowside
MOSFETs to prevent rapid output capacitor discharge during system
shutdown.
The ADP3121 is specified over the commercial temperature range
of 0°C to 85°C and is available in 8lead SOIC_N and 8lead LFCSP
packages.
Features
AllInOne Synchronous Buck Driver
Bootstrapped HighSide Drive
One PWM Signal Generates Both Drives
Anticross Conduction Protection Circuitry
Overvoltage Protection
OD for Disabling the Driver Outputs
Meets CPU VR Requirement when Used with FlexModet
Controller
These are PbFree Devices
Typical Applications
Multiphase Desktop CPU Supplies
Single Supply Synchronous Buck Converters
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MARKING
DIAGRAMS
8 SO8
1
D SUFFIX
CASE 75107
8
P3121
ALYW G
G
P3121A = Device Code
1
AL = Assembly Location
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
8
1
LFCSP8
MN SUFFIX
CASE 932AF
L7Q
#YWW
L7Q = Device Code
# = PbFree Package
Y = Year
WW = Work Week
PIN ASSIGNMENT
BST
IN
OD
VCC
DRVH
SWN
PGND
DRVL
ORDERING INFORMATION
Device
Package
Shipping
ADP3121JRZRL SOIC_N 2500/Tape & Reel
(PbFree)
ADP3121JCPZRL LFCSP_VD 5000/Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
February, 2010 Rev. 1
1
Publication Order Number:
ADP3121/D



ADP3121
ADP3121
ADP3121
IN 2
4 VCC
DELAY
LATCH
R1
R2 Q
S
OD 3
CMP
1V
CMP
VCC
6
CONTROL
LOGIC
DELAY
Figure 1. Block Diagram
12 V
D1
BST
1
CBST1
8 DRVH
SW
7
CBST2
RG
RBST
Q1
TO
INDUCTOR
DRVL
5
PGND
6
Q2
PIN DESCRIPTION
Pin No.
Pin Name
1 BST
2 IN
3 OD
4 VCC
5 DRVL
6 PGND
7 SW
8 DRVH
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds
this bootstrapped voltage for the highside MOSFET while it is switching.
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this
pin low turns on the lowside driver; pulling it high turns on the highside driver.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with an ~1 mF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched
voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
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