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AT91SAM7L64 Dataheets PDF



Part Number AT91SAM7L64
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description Microcontroller
Datasheet AT91SAM7L64 DatasheetAT91SAM7L64 Datasheet (PDF)

Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Access at Up to 15 MHz in Worst Case Conditions – 128-bit Read Acc.

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Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Access at Up to 15 MHz in Worst Case Conditions – 128-bit Read Access – Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time: 10 ms – 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production • Internal High-speed SRAM, Single-cycle Access at Maximum Speed – 6 Kbytes • 2 Kbytes Directly on Main Supply That Can Be Used as Backup SRAM • 4 Kbytes in the Core • Memory Controller (MC) – Enhanced Embedded Flash Controller, Abort Status and Misalignment Detection • Enhanced Embedded Flash Controller (EEFC) – Interface of the Flash Block with the 32-bit Internal Bus – Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface • Reset Controller (RSTC) – Based on Zero-power Power-on Reset and Fully Programmble Brownout Detector – Provides External Reset Signal Shaping and Reset Source Status • Clock Generator (CKGR) – Low-power 32 kHz RC Oscillator, 32 kHz On-chip Oscillator, 2 MHz Fast RC Oscillator and one PLL • Supply Controller (SUPC) – Minimizes Device Power Consumption – Manages the Different Supplies On Chip – Supports Multiple Wake-up Sources • Power Management Controller (PMC) – Software Power Optimization Capabilities, Including Active and Four Low Power Modes: • Idle Mode: No Processor Clock • Wait Mode: No Processor Clock, Voltage Regulator Output at Minimum • Backup Mode: Voltage Regulator and Processor Switched Off • Off (Power Down) Mode: Entire Chip Shut Down Except for Force Wake Up Pin (FWUP) that Re-activates the Device. 100 nA Current Consumption. • In Active Mode, Dynamic Power Consumption <30 mA at 36 MHz – Three Programmable External Clock Signals – Handles Fast Start Up AT91 ARM Thumb-based Microcontroller AT91SAM7L128 AT91SAM7L64 Preliminary . 6257A–ATARM–20-Feb-08 • Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected • Debug Unit (DBGU) – Two-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention • Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter • Windowed Watchdog (WDT) – 12-bit Key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter may be Stopped While the Processor is in Debug State or in Idle Mode • Real-time Clock (RTC) – Two Hundred Year Calendar with Alarm – Runs Off the Internal RC or Crystal Oscillator • Three Parallel Input/Output Controllers (PIOA, PIOB, PIOC) – Eighty Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up resistor and Synchronous Output • Eleven Peripheral DMA Controller (PDC) Channels • One Segment LCD Controller – Display Capacity of Forty Segments and Ten Common Terminals – Software Selectable LCD Output Voltage (Contrast) • Two Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Manchester Encoder/Decoder – Full Modem Line Support on USART1 • One Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects • One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master, Multi-Master and Slave Mode Support, All Atmel® Two-wire EEPROMs and I2C compatible Devices Supported – General Call Supported in Slave Mode • One 4-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os • SAM-BA® Boot Assistant – Default Boot Program – Interface with SAM-BA Graphic User Interface – In Application Programming Function (IAP) • IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins • Four High-current Drive I/O lines, Up to 4 mA Each • Power Supplies – Embedded 1.8V Regulator, Drawing up to 60 mA for the Core with Programmable Output Voltage – Single Supply 1.8V - 3.6V • Fully Stati.


AT91SAM7L128 AT91SAM7L64 AMS6101


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