ADCLK905 Datasheet (data sheet) PDF





ADCLK905 Datasheet, (ADCLK905 - ADCLK925) Ultrafast ECL Clock / Data Buffers

ADCLK905   ADCLK905  

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www.DataSheet4U.com Ultrafast SiGe ECL Clock/Data Buffers ADCLK905/ADCLK907/AD CLK925 TYPICAL APPLICATION CIRCUITS VRE F VT VCC FEATURES 95 ps propagation de lay 7.5 GHz toggle rate 60 ps typical o utput rise/fall 60 fs random jitter (RJ ) On-chip terminations at both input pi ns Extended industrial temperature rang e: −40°C to +125°C 2.5 V to 3.3 V p ower supply (VCC − VEE) D D Q Q 063 18-001 APPLICATIONS Clock and data sig nal restoration and level shifting Auto mated test equipment (ATE) High speed i nstrumentation High speed line receiver s Threshold detection Converter clockin g VEE Figure 1. ADCLK905 ECL 1:1 Cloc k/Data Buffer VREF 1 V T1 VCC

ADCLK905 Datasheet, (ADCLK905 - ADCLK925) Ultrafast ECL Clock / Data Buffers

ADCLK905   ADCLK905  
D1 D1 VEE VEE D2 D2 VCC VREF 2 06318-002 GENERAL DESCRIPTION The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock /data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silico n germanium (SiGe) bipolar process. The ADCLK905/ADCLK907/ADCLK925 feature ful l-swing emitter coupled logic (ECL) out put drivers. For PECL (positive ECL) op eration, bias VCC to the positive suppl y and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply. The buffer s offer 95 ps propagation delay, 7.5 GH z toggle rate, 10 Gbps data rate, and 6 0 fs random jitter (RJ). The inputs hav e center tapped, 100 Ω, on-chip termin ation resistors. A VREF pin is availabl e for biasing ac-coupled inputs. The EC L output stages are designed to directl y drive 800 mV each side into 50 Ω ter minated to VCC − 2 V for a total diff erential output swing of 1.6 V. The ADC LK905/ADCLK907/ADCLK925 are available i n 16-lead LFCSP packages. Q1 Q1 Q2 Q2 V T2 Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer VREF VT VCC Q1 Q1 D D Q2 06318-003 Q2 VEE Figure 3. AD CLK925 ECL 1:2 Clock/Data Fanout Buffer Rev. 0 Information furnished by Analo g Devices is believed to be accurate and reliable. Howe








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