ADCLK854 Datasheet (PDF)





ADCLK854 Datasheet - Low Power Clock Fanout Buffer

ADCLK854   ADCLK854  

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www.DataSheet4U.com 1.8 V, 12-LVDS/24-C MOS Output, Low Power Clock Fanout Buff er ADCLK854 FUNCTIONAL BLOCK DIAGRAM AD CLK854 VREF CLK0 CLK0 CLK1 CLK1 IN_SEL CTRL_A LVDS/ CMOS VS/2 LVDS/ CMOS OUT0 (OUT0A) OUT0 (OUT0B) OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) FEATURES 2 select able differential inputs Selectable LVD S/CMOS outputs Up to 12 LVDS

ADCLK854 Datasheet - Low Power Clock Fanout Buffer

ADCLK854   ADCLK854  
(1.2 GHz) or 24 CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation) 54 fs rms integrated jitter (12 kHz to 20 MHz) 100 fs rms additive broadband j itter 2.0 ns propagation delay (LVDS) 1 35 ps output rise/fall (LVDS) 70 ps out put-to-output skew (LVDS) Sleep mode Pi n programmable control 1.8 V power supp ly APPLICATIONS Low jitter clock distr ibution Clock and data signa








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