ADCLK846 Datasheet (PDF)





ADCLK846 Datasheet - 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

ADCLK846   ADCLK846  

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www.DataSheet4U.com 1.8 V, 6 LVDS/12 CM OS Outputs Low Power Clock Fanout Buffe r ADCLK846 FUNCTIONAL BLOCK DIAGRAM ADC LK846 LVDS/CMOS OUT0 (OUT0A) OUT0 (OUT0 B) VREF OUT1 (OUT1A) CLK CLK CTRL_A LVD S/CMOS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 ( OUT3A) OUT3 (OUT3B) OUT4 (OUT4A) CTRL_B SLEEP OUT4 (OUT4B) OUT5 (OUT5A) OUT5 ( OUT5B) 07226-001 FEATURES Selectable L VDS/CMOS outputs Up to 6 LVD

ADCLK846 Datasheet - 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

ADCLK846   ADCLK846  
S (1.2 GHz) or 12 CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation) 54 fs integrated jitter (12 kHz to 20 MHz) 100 fs additive broadband jitter 2 .0 ns propagation delay (LVDS) 135 ps o utput rise/fall (LVDS) 65 ps output-to- output skew (LVDS) Sleep mode Pin-progr ammable control 1.8 V power supply OUT 1 (OUT1B) APPLICATIONS Low jitter cloc k distribution Clock and dat








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