MAX3625A

19-4626; Rev 0; 5/09 www.DataSheet4U.com KIT ATION EVALU E L B A AVAIL Low-Jitter, Precision Clock Generator with Three Outputs General Description Features ♦ Crystal Oscillator Interface: 24.8MHz to 27MHz ♦ CMOS Input: Up to 320MHz ♦ Output Frequencies Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz 10G Fibre Channel: 159.375MHz, 318.75MHz ♦ Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.36psRMS (12kHz to 20MHz) ♦ Excellent Power-Supply Noise Rejection ♦ No External Loop Filter Capacitor Required MAX3625A The MAX3625A is a low-jitter, precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, 10G Fibre Channel, and other networking applications. Maxim’s proprietary PLL design features ultra-low jitter and excellent power-supply noise rejection, minimizing design risk for network equipment. The MAX3625A has three LVPECL outputs. Selectable output dividers and a selectable feedback divider allow a range of output frequencies. Applications Ethernet Networking Equipment Fibre Channel Storage Area Network Pin Configuration and Typical Application Circuit appear at end of data sheet. PART MAX3625ACUG+ Ordering Information TEMP RANGE 0°C to +70°C PIN-PACKAGE 24 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. Block Diagram IN_SEL MR BYPASS SELA[1:0] SELA[1:0] SELB[1:0] FB_SEL BYPASS QA_OE RESET LOGIC/POR RESET DIVIDER NA L...