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LF3310 Dataheets PDF



Part Number LF3310
Manufacturers LOGIC Devices Incorporated
Logo LOGIC Devices Incorporated
Description Horizontal / Vertical Digital Image Filter
Datasheet LF3310 DatasheetLF3310 Datasheet (PDF)

LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter DESCRIPTION The LF3310 is a two-dimensional digital image filter capable of filtering data at real-time video rates. The device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for two-dimensional filtering. The input, coefficient, and output data are all 12-bits and in two’s complement format. The horizontal .

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LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter DESCRIPTION The LF3310 is a two-dimensional digital image filter capable of filtering data at real-time video rates. The device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for two-dimensional filtering. The input, coefficient, and output data are all 12-bits and in two’s complement format. The horizontal filter is designed to take advantage of symmetric coefficient sets. When symmetric coefficient sets are used, the horizontal filter can be configured as a 16-tap FIR filter. When asymmetric coefficient sets are used, it can be configured as an 8-tap FIR filter. The vertical filter is an 8-tap FIR filter with all required line buffers contained on-chip. The line buffers can store video lines with lengths from 4 to 3076 pixels. Horizontal filter Interleave/Decimation Registers (I/D Registers) and the vertical filter line buffers allow interleaved data to be fed directly into the device and filtered without separating the data into individual data streams. The horizontal filter can handle a maximum of sixteen data sets interleaved together. The vertical filter can handle interleaved video lines which contain 3076 or less data values. The I/D Registers and horizontal accumulator facilitate using decimation to increase the number of filter taps in the horizontal filter. Decimation of up to 16:1 is supported. The device has on-chip storage for 256 horizontal coefficient sets and 256 vertical coefficient sets. Each filter’s coefficients are loaded independently of each other allowing one filter’s coefficients to be updated without affecting the other filter’s coefficients. In addition, a horizontal or vertical coefficient set can be updated independently from the other coefficient sets in the same filter. FEATURES u 83 MHz Data Rate u 12-bit Data and Coefficients u On-board Memory for 256 Horizontal and Vertical Coefficient Sets u LF InterfaceTM Allows All 512 Coefficient Sets to be Updated Within Vertical Blanking u Selectable 12-bit Data Output with User-Defined Rounding and Limiting u Seven 3K x 12-bit, Programmable Two-Mode Line Buffers u 16 Horizontal Filter Taps u 8 Vertical Filter Taps u Two Operating Modes: Dimensionally Separate and Orthogonal u Supports Interleaved Data Streams u Horizontal Filter Supports Decimation up to 16:1 for Increasing Number of Filter Taps u 3.3 Volt Power Supply u 5 Volt Tolerant I/O u 144 Lead PQFP LF3310 BLOCK DIAGRAM 12 DIN11-0 16-TAP HORIZONTAL FILTER 256 COEFFICIENT SET STORAGE 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 8-TAP VERTICAL FILTER 256 COEFFICIENT SET STORAGE 12 3K LINE BUFFER DOUT11-0 Video Imaging Products 1 11/08/2001-LDS.3310-H I/D REGISTERS FIGURE 1. E O I DATA REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 TXFR DATA DELAY 12 1-16 1-16 1-16 1-16 1-16 1-16 1-16 DEVICES INCORPORATED 12 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 A B A B A B A B A B A B A B 1-16 A DIN11-0 B HCF11-0 HPAUSE HLD 12 H Coef Bank 0 CONFIGURATION AND CONTROL REGISTERS 12 H Coef Bank 1 12 12 HORIZONTAL LF INTERFACE 12 VCF11-0 H Coef Bank 7 VPAUSE VLD VERTICAL LF INTERFACE H Coef Bank 6 HCEN 12 H Coef Bank 2 12 H Coef Bank 5 8 HCA7-0 VCEN 12 H Coef Bank 3 12 H Coef Bank 4 8 VCA7-0 25 25 25 25 25 25 25 25 V Coef Bank 7 27 V Coef Bank 6 V Coef Bank 5 V Coef Bank 4 27 LF3310 FUNCTIONAL BLOCK DIAGRAM 12 12 24 12 12 12 2 HACC 12 26 12 24 24 "0" 32 12 24 DATA DELAY 12 24 32 12 24 26 12 24 "0" 32 32 4 HRSL3-0 VERTICAL ROUND SELECT LIMIT HORIZONTAL ROUND SELECT LIMIT 12 24 12 12 12 12 12 V Coef Bank 0 V Coef Bank 1 V Coef Bank 2 V Coef Bank 3 OE 4 VACC VRSL3-0 12 DOUT11-0 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer HSHEN VSHEN Horizontal / Vertical Digital Image Filter Video Imaging Products LF3310 11/08/2001-LDS.3310-H CLK LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter FIGURE 2. INPUT FORMATS Input Data 11 10 9 –211 210 29 (Sign) SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. Inputs DIN11-0 — Data Input DIN11-0 is the 12-bit registered data input port. Data is latched on the rising edge of CLK. HCF11-0 — Horizontal Coefficient Input HCF11-0 is used to load data into the horizontal coefficient banks and the Configuration/Control Registers. Data present on HCF11-0 is latched into the Horizontal LF InterfaceTM on the rising edge of CLK when HLD is LOW (see the LF InterfaceTM section for a full discussion). HCA7-0 — Horizontal Coefficient Address HCA7-0 determines which row of data in the horizontal coefficient banks is fed to the multipliers in the horizonta.


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