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RoboClockII™ Junior, CY7B9930V, CY7B9940V
High Speed Multifrequency PLL Clock Buffer
Features
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12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V) input/output operation Matched pair output skew < 200 ps Zero input-to-output delay 10 LVTTL 50% duty-cycle outputs capable of driving 50ω terminated lines Commercial temperature range with eight outputs at 200 MHz Industrial temperature range with eight outputs at 200 MHz 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot insertable reference inputs Multiply ratios of (1–6, 8, 10, 12) Operation up to 12x input frequency Individual output bank disable for aggressive power management and EMI reduction Output high impedance option for testing purposes Fully integrated PLL with lock indicator Low cycle-to-cycle jitter (<100 ps peak-peak)
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Single 3.3V ± 10% supply 44-pin TQFP package
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multifrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer or communication systems. Ten configurable outputs can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in three banks. The FB feedback bank consists of two outputs, which allows divide-by functionality from 1 to 12. Any one of these ten outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerance feature that allows smooth change over to secondary clock source, when the primary clock source is not in operation. The reference inputs are configurable to accommodate both LVTTL or differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout.
Block Diagram
FBKA Phase Freq. Detector VCO Control Logic Divide Generator LOCK Filter
REFA+ REFA– REFB+ REFB– REFSEL
FS Output_Mode
3 3
Feedback Bank
FBDS0 FBDS1
3 3
Divide Matrix
QFA0 QFA1
2QA0 2QA1
Bank 2
DIS2
2QB0 2QB1 1QA0 1QA1
Bank 1
DIS1
1QB0 1QB1
Cypress Semiconductor Corporation Document Number: 38-07271 Rev. *C
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198 Champion Court
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San Jose, CA 95134-1709
• 408-943-2600 Revised August 8, 2007
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RoboClockII™ Junior, CY7B9930V, CY7B9940V
Divide Matrix
The Divide Matrix is comprised of three independent banks: two banks of clock outputs and one bank for feedback. Each clock output bank has two pairs of low-skew, high fanout output buffers ([1:2]Q[A:B][0:1]), and an output disable (DIS[1:2]). The feedback bank has one pair of low-skew, high fanout output buffers (QFA[0:1]). One of these outputs may connect to the selected feedback input (FBKA+). This feedback bank also has two divider function selects FBDS[0:1]. The divide capabilities for each bank are shown in.