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BUK9MJJ-55PTT Dataheets PDF



Part Number BUK9MJJ-55PTT
Manufacturers NXP
Logo NXP
Description Dual TrenchPLUS Logic Level FET
Datasheet BUK9MJJ-55PTT DatasheetBUK9MJJ-55PTT Datasheet (PDF)

BUK9MJJ-55PTT www.DataSheet4U.com Dual TrenchPLUS logic level FET Rev. 01 — 14 May 2009 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes. 1.2 Features and benefits „ Integrated current sensors „ Integrated temperatur.

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BUK9MJJ-55PTT www.DataSheet4U.com Dual TrenchPLUS logic level FET Rev. 01 — 14 May 2009 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes. 1.2 Features and benefits „ Integrated current sensors „ Integrated temperature sensors 1.3 Applications „ Lamp switching „ Motor drive systems „ Power distribution „ Solenoid drivers 1.4 Quick reference data Table 1. Quick reference Conditions VGS = 5 V; ID = 10 A; Tj = 25 °C; see Figure 16; see Figure 17 Tj = 25 °C; VGS = 5 V; see Figure 18 Tj = 25 °C; VGS = 0 V; ID = 250 µA Min Typ 13 Max 15 Unit mΩ Symbol Parameter RDSon drain-source on-state resistance ratio of drain current to sense current Static characteristics, FET1 and FET2 ID/Isense 5850 55 6500 - 7150 - A/A V V(BR)DSS drain-source breakdown voltage NXP Semiconductors www.DataSheet4U.com BUK9MJJ-55PTT Dual TrenchPLUS logic level FET 2. Pinning information Table 2. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pinning information Symbol G1 IS1 D1 A1 C1 G2 IS2 D2 A2 C2 D2 KS2 S2 S2 D2 D1 KS1 S1 S1 D1 Description gate 1 current sense 1 drain 1 anode 1 cathode 1 gate 2 current sense 2 drain 2 anode 2 cathode 2 drain 2 Kelvin source 2 source 2 source 2 drain 2 drain 1 Kelvin source 1 source 1 source 1 drain 1 1 10 20 11 D1 A1 D2 A2 Simplified outline Graphic symbol FET1 FET2 SOT163-1 (SO20) G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2 003aaa745 3. Ordering information Table 3. Ordering information Package Name BUK9MJJ-55PTT SO20 Description plastic small outline package; 20 leads; body width 7.5 mm Version SOT163-1 Type number BUK9MJJ-55PTT_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 2 of 15 NXP Semiconductors www.DataSheet4U.com BUK9MJJ-55PTT Dual TrenchPLUS logic level FET 4. Limiting values Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature Tsp = 25 °C; VGS = 5 V; see Figure 3; see Figure 2; [1][2] Tsp = 100 °C; VGS = 5 V; see Figure 2; Tsp = 25 °C; tp ≤ 10 µs; pulsed; see Figure 3 Tsp = 25 °C; see Figure 1 [1][2] Conditions 25 °C < Tj < 150 °C RGS = 20 kΩ; 25 °C < Tj < 150 °C Min -15 -55 -55 Max 55 55 15 12.9 8.1 230 4.5 150 150 100 Unit V V V A A A W °C °C V In accordance with the Absolute Maximum Rating System (IEC 60134). Limiting Values, FET1 and FET2 Visol(FET-TSD) FET to temperature sense diode isolation voltage Source-drain diode, FET1 and FET2 IS ISM EDS(AL)S source current peak source current Tsp = 25 °C; tp ≤ 10 µs; pulsed; Tsp = 25 °C [3][4] [5] [2][1] - 6.5 230 527 A A mJ Avalanche ruggedness, FET1 and FET2 non-repetitive ID = 12.9 A; Vsup ≤ 55 V; VGS = 5 V; Tj(init) = 25 °C; drain-source avalanche unclamped; see Figure 4; energy electrostatic discharge voltage HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16 and 20 to pins 1, 2, 17, 18 and 19 shorted HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11 and 15 to pins 6, 7, 12,13 and 14 shorted HBM; C = 100 pF; R = 1.5 kΩ; all pins [1] [2] [3] [4] [5] Single device conducting. Current is limited by chip power dissipation rating. Single-pulse avalanche rating limited by maximum junction temperature of 150 °C. Repetitive rating defined in avalanche rating figure. Refer to application note AN10273 for further information. Electrostatic discharge, FET1 and FET2 VESD 4 4 0.15 kV kV kV BUK9MJJ-55PTT_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 3 of 15 NXP Semiconductors www.DataSheet4U.com BUK9MJJ-55PTT Dual TrenchPLUS logic level FET 120 Pder (%) 80 003aab388 15 ID (A) 003aab887 10 40 5 0 0 50 100 150 Tsp 200 (°C) 0 0 50 100 150 Tsp (°C) 200 Fig 2. Fig 1. Normalized total power dissipation as a function of solder point temperature, FET1 and FET2 Continuous drain current as a function of solder point temperature, FET1 and FET2 103 ID (A) 102 Limit RDSon = VDS / ID 003aab894 tp = 10 μ s 100 μ s 10 1 ms 10 ms 1 DC 10-1 100 ms 10-2 10-1 1 10 VDS (V) 102 Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and FET2 BUK9MJJ-55PTT_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 14 May 2009 4 of 15 NXP Semiconductors w w w . D a t a S h e e t 4 U . c o m BUK9MJJ-55PTT Dual TrenchPLUS logic level FET 102 IAL (A) 003aab924 (1) 10 (2) 1 (3) 10-1 10-3 10-2 10-1 1 tAL (ms) 10 Fig 4. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2 5. Thermal characteristics Table 5. Symbol Rth(j-sp) Rth(j-a) Thermal characteristics Parameter Conditions Min .


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