Document
DS64EV100 Programmable Single Equalizer
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November 9, 2007
DS64EV100 Programmable Single Equalizer
General Description
The DS64EV100 programmable equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter for NRZ data channel. The DS64EV100 is optimized for operation up to 10 Gbps for both cables and FR4 traces. The equalizer channel has eight levels of input equalization that can be programmed by three control pins. The equalizer supports both AC and DC-coupled data paths for long run length data patterns such as PRBS-31, and balanced codes such as 8b/10b. The device uses differential current-mode logic (CML) inputs and outputs, and is available in a 3 mm x 4 mm 14-pin leadless LLP package. Power is supplied from either a 2.5V or 3.3V supply.
Features
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Equalizes up to 24 dB loss at 10 Gbps Equalizes up to 22 dB loss at 6.4 Gbps 8 levels of programmable equalization Operates up to 10 Gbps with 30” FR4 traces Operates up to 6.4 Gbps with 40” FR4 traces 0.175 UI residual deterministic jitter at 6.4 Gbps with 40” FR4 traces Single 2.5V or 3.3V power supply Supports AC or DC-Coupling with wide input commonmode Low power consumption: 100 mW Typ at 2.5V Small 3 mm x 4 mm 14-pin LLP package >8 kV HBM ESD -40 to 85°C operating temperature range
Simplified Application Diagram
20196401
© 2007 National Semiconductor Corporation
201964
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DS64EV100
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Pin Diagram
20196402
Top View 3mm x 4mm 14-Pin LLP Package Order number DS64EV100 See NS Package Number SDA14A
Pin Descriptions
Pin Name Pin Number I/O, Type I, CML Description
HIGH SPEED DIFFERENTIAL I/O IN+ IN− OUT+ OUT− BST_2 BST_1 BST_0 POWER VDD GND Exposed Pad OTHER NC 1 Reserved. Do not connect. 5 2, 6, 9, 10, 13 PAD I, Power VDD = 2.5V ±5% or 3.3V ±10%. VDD pins should be tied to VDD plane through low inductance path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes. I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance path. I, Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board. 3 4 12 11 14 7 8 Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN+ and IN-.
O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT+ to VDD and OUT- to VDD. I, CMOS BST_2, BST_1, and BST_0 select the equalizer strength for EQ channel 1. BST_2 is internally pulled high. BST_1 and BST_0 are internally pulled low.
EQUALIZATION CONTROL
Note: I = Input, O = Output
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DS64EV100
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specificat.