74HCT03 Datasheet (data sheet) PDF





74HCT03 Datasheet, Quad 2-input NAND gate

74HCT03   74HCT03  

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INTEGRATED CIRCUITS www.DataSheet4U.com DATA SHEET For a complete data sheet, please also download: • The IC06 74HC /HCT/HCU/HCMOS Logic Family Specificati ons • The IC06 74HC/HCT/HCU/HCMOS Log ic Package Information • The IC06 74H C/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT03 Quad 2-input NAND gate Prod uct specification File under Integrate d Circuits, IC06 December 1990 Philips Semiconductors www.DataSheet4U.com Pr oduct specification Quad 2-input NAND gate FEATURES • Level shift capabili ty • Output capability: standard (ope n drain) • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT03 are high-spe ed Si-gate CMOS devices and are pin compa

74HCT03 Datasheet, Quad 2-input NAND gate

74HCT03   74HCT03  
tible with low power Schottky TTL (LSTTL ). They are specified in compliance wit h JEDEC standard no. 7A. QUICK REFERENC E DATA GND = 0 V; Tamb = 25 °C; tr = t f = 6 ns 74HC/HCT03 The 74HC/HCT03 pro vide the 2-input NAND function. The 74H C/HCT03 have open-drain N-transistor ou tputs, which are not clamped by a diode connected to VCC. In the OFF-state, i. e. when one input is LOW, the output ma y be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW l evel shifter. For digital operation and OR-tied output applications, these dev ices must have a pull-up resistor to es tablish a logic HIGH level. TYPICAL SY MBOL tPZL/ tPLZ CI CPD Notes 1. CPD is used to determine the dynamic power dis sipation (PD in µW): PD = CPD × VCC2 fi + ∑ (CL × VCC2 × fo) + ∑ (VO 2/RL) × duty factor LOW, where: fi = i nput frequency in MHz fo = output frequ ency in MHz VO = output voltage in V CL = output load capacitance in pF VCC = supply voltage in V RL = pull-up resist or in MΩ ∑ (CL × VCC2 × fo) = sum of outputs ∑ (VO2/RL) = sum of outpu ts 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GN D to VCC − 1.5 V 3. The given value o f CPD is obtained with: CL = 0 pF and R L = ∞ ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Informa








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