IP100ALF

www.DataSheet4U.com IP100A LF Preliminary Data Sheet Integrated 10/100 Ethernet MAC + PHY Features Single chip 10/100BASE, half or full duplex Ethernet Media Access Controller IEEE 802.3 compliant 100BASE-TX/100BASE-FX/10BASE-T PCI Bus master scatter/gather DMA on any byte boundary Full operation with PCI Clock from 25 MHz to 33 MHz PCI Revision 2.2 compliant On-chip transmit and receive FIFO buffers On-chip LED drivers Power management capabilities for ACPI 1.0 compliant systems WakeOnLAN support Management statistics gathering IP multicast receive and filter support using 64 bit hash table Transmit polling Auto pad insertion for short packets Programmable minimum Inter Packet Gap Supports auto MDI-MDIX function Smart Cable Analyzer (SCA) Support Capable of using 93C46 EEPROM On-chip crystal oscillator On-chip voltage regulator 2.5/3.3V CMOS with 5V tolerant I/O 0.25µm technology 128-pin PQFP Support Lead Free package (Please refer to the Order Information) General Description The IP100A LF is a single-chip, full duplex, 10/100Mbps Ethernet MAC + PHY incorporating a 32-bit PCI with bus master support. The IP100A LF is designed for use in a variety of applications including workstation NICs, PC motherboards, and other systems utilizing a PCI bus that require network connectivity to an Ethernet or Fast Ethernet LAN. The IP100A LF includes a PCI bus interface unit, IEEE 802.3 compliant MAC, transmit and receive FIFO buffers, IEEE 802.3 compliant 100BASE-TX, 10BASE-T, and 100...