Document
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
Rev. 2 — 3 October 2011
Product data sheet
1. General description
The PCA9675 provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus family.
The PCA9675 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus (Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without the need for bus buffers, higher total package sink capacity (400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and more device addresses (64 versus 8) are available to allow many more devices on the bus without address conflicts.
The device consists of a 16-bit quasi-bidirectional port and an I2C-bus interface. The PCA9675 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs.
It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. The internal Power-On Reset (POR) or software reset sequence initializes the I/Os as inputs.
2. Features and benefits
1 MHz I2C-bus interface Compliant with the I2C-bus Fast and Standard modes SDA with 30 mA sink capability for 4000 pF buses 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 16-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 400 mA Active LOW open-drain interrupt output 64 programmable slave addresses using 3 address pins Readable device ID (manufacturer, device type, and revision) Low standby current 40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
Packages offered: SO24, TSSOP24, HVQFN24, DHVQFN24
3. Applications
LED signs and displays Servers Industrial control PLCs Cellular telephones Gaming machines Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information
Type number Topside mark
Package Name
Description
PCA9675D PCA9675D SO24
plastic small outline package; 24 leads; body width 7.5 mm
PCA9675PW PCA9675PW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm
PCA9675BQ 9675
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm
PCA9675BS 9675
HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm
Version SOT137-1 SOT355-1
SOT815-1
SOT616-1
PCA9675
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 October 2011
© NXP B.V. 2011. All rights reserved.
2 of 34
NXP Semiconductors
5. Block diagram
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
INT
AD0 AD1 AD2 SCL SDA
PCA9675
INTERRUPT LOGIC
INPUT FILTER
I2C-BUS CONTROL
LP FILTER
SHIFT REGISTER 16 BITS
I/O PORT
P00 to P07 P10 to P17
VDD
POWER-ON RESET
VSS
Fig 1. Block diagram of PCA9675
write pulse read pulse
002aab627
write pulse data from Shift Register
power-on reset
DQ
FF
CI S
Itrt(pu)
IOH
100 μA
IOL
VDD
P00 to P07 P10 to P17 VSS
read pulse data to Shift Register
DQ
FF
CI S
to interrupt logic
002aab631
Fig 2. Simplified schematic diagram of P00 to P17
PCA9675
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 October 2011
© NXP B.V. 2011. All rights reserved.
3 of 34
NXP Semiconductors
6. Pinning information
6.1 Pinning
PCA9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
INT 1 AD1 2 AD2 3 P00 4 P01 5 P02 6 P03 7 P04 8 P05 9 P06 10 P07 11 VSS 12
PCA9675D
24 VDD 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 13 P10
002aab628
Fig 3. Pin configuration for SO24
INT 1 AD1 2 AD2 3 P00 4 P01 5 P02 6 P03 7 P04 8 P05 9 P06 10 P07 11 VSS 12
PCA9675PW
24 VDD 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 13 P10
002aab629
Fig 4. Pin configuration for TSSOP24
1 INT 24 VDD
24 AD2 23 AD1 22 INT 21 VDD 20 SDA 19 SCL
terminal 1 index area
P00 1 P01 2 P02 3 P03 4 P04 5 P05 6
PCA9675BS
18 AD0 17 P17 16 P16 15 P15 14 P14 13 P13
terminal 1 index area
AD1 2 AD2 3 P00 4 P01 5 P02 6 P03 7 P04 8 P05 9 P06 10 P07 11
PCA9675BQ
23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16.