CS2100-CP Datasheet (data sheet) PDF





CS2100-CP Datasheet - Fractional-N Clock Multiplier

CS2100-CP   CS2100-CP  

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www.DataSheet4U.com CS2100-CP Fractiona l-N Clock Multiplier General Descriptio n The CS2100-CP is an extremely versati le system clocking device that utilizes a programmable phase lock loop. The CS 2100-CP is based on a hybrid analog-dig ital PLL architecture comprised of a un ique combination of a Delta-Sigma Fract ional-N Frequency Synthesizer and a Dig ital PLL. This architecture

CS2100-CP Datasheet - Fractional-N Clock Multiplier

CS2100-CP   CS2100-CP  
allows for generation of a low-jitter cl ock relative to an external noisy synch ronization clock at frequencies as low as 50 Hz. The CS2100-CP supports both I ²C and SPI for full software control. The CS2100-CP is available in a 10-pin MSOP package in Commercial (-10°C to + 70°C) grade. Customer development kits are also available for device evaluati on. Please see “Ordering Inform








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