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Vin LDO. FAN2564 Datasheet

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Vin LDO. FAN2564 Datasheet






FAN2564 LDO. Datasheet pdf. Equivalent




FAN2564 LDO. Datasheet pdf. Equivalent





Part

FAN2564

Description

300mA Low Vin LDO



Feature


FAN2564 — 300mA Low VIN LDO for Digita l Applications April 2011 FAN2564 300 mA Low VIN LDO for Digital Applications Features  Input Voltage 1.65V to 3 .6V  Guaranteed 300mA Output  Hig h Initial Output Voltage Accuracy: ±1%  Fixed Output Voltage options from 1.2V to 2.8V  Very Low Dropout: 100m V at 300mA  45µA Quiescent Current at No Load  Low Output Noise of 1.
Manufacture

Fairchild Semiconductor

Datasheet
Download FAN2564 Datasheet


Fairchild Semiconductor FAN2564

FAN2564; 00µVRMS  Inrush Current Controlled t o Less Than 500mA  PSRR of 60dB at 1 kHz  100µs Startup Time  Stable with Ceramic Capacitors  Thermal and Short-Circuit Protection  4-bump WL CSP, 0.5mm Pitch  6-pin 2 x 2mm UMLP Applications  Post Regulator  Ce ll Phones and Smart Phones  WLAN, 3G , and 4G Data Cards  PMP and MP3 Pla yers Description The FAN2564 operates fro.


Fairchild Semiconductor FAN2564

m a minimum input of 1.65V and provides outputs as low as 1.2V. Output current is guaranteed to 300mA, making this reg ulator ideal for digital loads. The uni que low input voltage capability and ve ry low dropout make this device an idea l post regulator to a synchronous buck regulator. In this configuration, accur ate low voltage regulation is provided without the ineffi.


Fairchild Semiconductor FAN2564

ciencies typically related to linear reg ulators. The enable pin can be used to initiate shutdown mode, where the opera ting current falls to an extremely low 10nA, typically. The FAN2564 is designe d to be stable with spacesaving ceramic capacitors as small as 0402 case size. The FAN2564 is available in 4-bump 0.5 mm pitch waferlevel chip-scale package (WLCSP) and a 6-le.

Part

FAN2564

Description

300mA Low Vin LDO



Feature


FAN2564 — 300mA Low VIN LDO for Digita l Applications April 2011 FAN2564 300 mA Low VIN LDO for Digital Applications Features  Input Voltage 1.65V to 3 .6V  Guaranteed 300mA Output  Hig h Initial Output Voltage Accuracy: ±1%  Fixed Output Voltage options from 1.2V to 2.8V  Very Low Dropout: 100m V at 300mA  45µA Quiescent Current at No Load  Low Output Noise of 1.
Manufacture

Fairchild Semiconductor

Datasheet
Download FAN2564 Datasheet




 FAN2564
April 2011
FAN2564
300mA Low VIN LDO for Digital Applications
Features
Input Voltage 1.65V to 3.6V
Guaranteed 300mA Output
High Initial Output Voltage Accuracy: ±1%
Fixed Output Voltage options from 1.2V to 2.8V
Very Low Dropout: 100mV at 300mA
45µA Quiescent Current at No Load
Low Output Noise of 100µVRMS
Inrush Current Controlled to Less Than 500mA
PSRR of 60dB at 1kHz
100µs Startup Time
Stable with Ceramic Capacitors
Thermal and Short-Circuit Protection
4-bump WLCSP, 0.5mm Pitch
6-pin 2 x 2mm UMLP
Applications
Post Regulator
Cell Phones and Smart Phones
WLAN, 3G, and 4G Data Cards
PMP and MP3 Players
Description
The FAN2564 operates from a minimum input of 1.65V
and provides outputs as low as 1.2V. Output current is
guaranteed to 300mA, making this regulator ideal for
digital loads.
The unique low input voltage capability and very low
dropout make this device an ideal post regulator to a
synchronous buck regulator. In this configuration, accu-
rate low voltage regulation is provided without the ineffi-
ciencies typically related to linear regulators.
The enable pin can be used to initiate shutdown mode,
where the operating current falls to an extremely low
10nA, typically.
The FAN2564 is designed to be stable with space-
saving ceramic capacitors as small as 0402 case size.
The FAN2564 is available in 4-bump 0.5mm pitch wafer-
level chip-scale package (WLCSP) and a 6-lead 2 x
2mm ultra-thin molded leadless package (UMLP).
Typical Application Circuit
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
Figure 1. Typical Application Circuit
www.fairchildsemi.com




 FAN2564
Ordering Information
Part Number Output Voltage(1) Temperature Range
Package
Packing Method
FAN2564UC12X
FAN2564UC13X
FAN2564UC15X
FAN2564UC18X
FAN2564UC25X
FAN2564UMP12X
FAN2564UMP13X
FAN2564UMP15X
FAN2564UMP18X
1.2
1.3
1.5
1.8
2.5
1.2
1.3
1.5
1.8
–40 to 85°C
WLCSP-4 0.5mm Pitch Tape and Reel
–40 to 85°C
6 Lead UMLP 2 x 2mm Tape and Reel
Notes:
1. Other voltage options available upon request. Contact a Fairchild representative.
Block Diagram
Figure 2. Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
2
www.fairchildsemi.com




 FAN2564
Pin Configuration
GN A1 A2 EN
VOU B1 B2 VIN
EN A2 A1 GND
VIN B2 B1 VOU
Figure 3. WLCSP Bumps Facing Down
Figure 4. WLCSP, Bumps Facing Up
EN 1
6 GND
NC 2 (AGND) 5 NC
VIN 3
4 VOUT
Figure 5. UMLP, Leads Facing Down
Pin Definitions
Pin #
WLCSP UMLP
A1 6
B1 4
B2 3
A2 1
5
2
Name
GND
VOUT
VIN
EN
NC
NC
Description
Ground. Power and IC ground. All signals are referenced to this pin.
VOUT. Connect to output voltage.
Input Voltage. Connect to input power source.
Enable. The device is in shutdown mode when voltage to this pin is <0.4V and
enabled when >0.95V.
No connect.
No connect.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
3
www.fairchildsemi.com






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