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ProcessorPM-POWR605
In-System Programmable Power Supply Supervisor, Reset Generator and Watchdog Timer
Preliminary Data Sheet DS1034
TM
April 2009
Features
■ Precision Programmable Threshold Monitors, Threshold Accuracy 0.7%
• Simultaneously monitors up to six power supplies • Programmable analog trip points (1% step size; 192 steps) • Programmable glitch filter • Power-off detection (75mV)
Application Block Diagram
Input Power Supply
DC-DC #1 Manual Reset In
DC-DC #2
DC-DC #n
■ Embedded Programmable Timers
• Four independent timers • 32µs to 2 second intervals for timing sequences
Power Supply Bus
■ Embedded PLD for Logical Control
• Rugged 16-macrocell CPLD architecture • 81 product terms / 28 inputs • Implements state machines and combinatorial functions
Voltage Supervisor Reset Generator
Interrupt – Power Fail CPU_Reset_in WDT Trigger Interrupt – WDT
Watchdog Timer
■ Power-Down Mode ICC < 10µA ■ Digital I/O
• Two dedicated digital inputs • Five programmable digital I/O pins
Power Down
ProcessorPMPOWR605
Power Up/Down Control
CPU / uProcessor
■ Wide Supply Range (2.64V to 3.96V)
• In-system programmable through JTAG • Industrial temperature range: -40°C to +85°C • 24-pin QFN package, lead-free option
Description
Lattice’s Power Manager II ProcessorPM-POWR605 is a general-purpose power-supply monitor, reset generator and watchdog timer, incorporating both in-system programmable logic and analog functions implemented in non-volatile E2CMOS® technology. The ProcessorPMPOWR605 device provides six independent analog input channels to monitor power supply voltages. Two general-purpose digital inputs are also provided for miscellaneous control functions. The ProcessorPM-POWR605 provides up to five open drain digital outputs that can be used for controlling DCDC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and generalpurpose logic interface functions. The five digital, open drain outputs can optionally be configured as digital inputs to sense more input signals as needed, such as manual reset, etc.
The diagram above shows how a ProcessorPMPOWR605 is used in a typical application. It controls power to the microprocessor system, generates the CPU reset and monitors critical power supply voltages, generating interrupts whenever faults are detected. It also provides a watchdog timer function to detect CPU operating and bus timeout errors. The ProcessorPM-POWR605 incorporates a 16-macrocell CPLD. Figure 1 shows the analog input comparators and digital inputs used as inputs to the CPLD array. The digital output pins providing the external control signals are driven by the CPLD. Four independently programmable timers also interface with the CPLD and can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder™, an easy-to-learn language integrated into the PACDesigner® software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs.
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Figure 1. ProcessorPM-POWR605 Block Diagram
VCC
ProcessorPM-POWR605 Data Sheet
ProcessorPM-POWR605
Power Down Logic IN1_PWRDN IN2 VMON1 6 Analog Voltage Monitor Inputs VMON2 VMON3 VMON4 VMON5 VMON6 PLD 16 Macrocells 28 Inputs IN_OUT1 IN_OUT2 IN_OUT3 IN_OUT4 IN_OUT5
4 Timers
JTAG Interface
GND
VCCJ
TDO
TDI
TCK
TMS
Pin Descriptions
Number 8, 9 20 19 18 17 15 22 21 12 13 11 14 3, 16 10 1 2 Name GND IN_OUT1 IN_OUT2 IN_OUT3 IN_OUT4 IN_OUT5 IN1_PWRDN IN2 TCK TDI TDO TMS VCC VCCJ VMON1 VMON2 Ground Digital Input9, 10 Open Drain Output2 Digital Input9, 10 Open Drain Output2 Digital Input9, 10 Open Drain Output2 Digital Input Digital Input
9, 10
Pin Type
Voltage Range Ground 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V3 0V to 5.5V3 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 2.64V to 3.96V 2.25V to 3.6V -0.3V to 5.9V8 -0.3V to 5.9V8 Ground1 PLD Input 3
Description
Open Drain Output 3 PLD Input 4 Open Drain Output 4 PLD Input 5 Open Drain Output 5 PLD Input 6 Open Drain Output 6 PLD Input 7 Open Drain Output 7 PLD Logic Input 1.4, 5 When not used, this pin should be pulled down with a 10kΩ resistor. PLD Logic Input 2. When not used, this pin should be tied to GND. JTAG Test Clock Input JTAG Test Data In - Internal Pull-up JTAG Test Data Out JTAG Test Mode Select - Internal Pull-up Power Supply6 VCC for JTAG Logic Interface Pins7 Voltage Monitor Input 1 Voltage Monitor Input 2
Open Drain Output2
9, 10
Open Drain Output2 Digital Input10 Digital Input10 Digital Input Digi.