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XR16M564 Dataheets PDF



Part Number XR16M564
Manufacturers Sipex Corporation
Logo Sipex Corporation
Description 1.62V TO 3.63V Quad UART
Datasheet XR16M564 DatasheetXR16M564 Datasheet (PDF)

XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO www.DataSheet4U.com MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XR16M5641 (M564) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and contro.

  XR16M564   XR16M564


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XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO www.DataSheet4U.com MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XR16M5641 (M564) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M564 is available in a 48-pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48 and 68 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16M564IV (64-pin) offers three state interrupt output while the XR16M564DIV provides continuous interrupt output. The XR16M564 is compatible with the industry standard ST16C554 and ST16C654/ 654D. NOTE: 1 Covered by U.S. Patent #5,649,122. FEATURES • Pin-to-pin compatible with ST16C454, ST16C554, TI’s TL16C754B and NXP’s SC16C754B • Intel or Motorola Data Bus Interface select • Four independent UART channels ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register Set Compatible to 16C550 Data rates of up to 16 Mbps 32 byte Transmit FIFO 32 byte Receive FIFO with error tags 4 Selectable TX and RX FIFO Trigger Levels Automatic Hardware (RTS/CTS) Flow Control Automatic Software (Xon/Xoff) Flow Control Programmable Xon/Xoff characters Wireless Infrared (IrDA 1.0) Encoder/Decoder Full modem interface • 1.62V to 3.63V supply operation • Sleep Mode with automatic wake-up • Crystal oscillator or external clock input APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FIGURE 1. XR16M564 BLOCK DIAGRAM 1.62V to 3.6V VCC GND UART Channel A 32 Byte TX FIFO TX & RX IR ENDEC A2:A0 D7:D0 IOR# IOW# CSA# CSB# CSC# CSD# INTA INTB INTC INTD TXRDY# A-D RXRDY # A-D Reset 16/68# INTSEL CLKSEL UART Regs BRG TXA, RXA, DTRA#, DSRA #, RTSA#, CTSA#, CDA#, RIA# 32 Byte RX FIFO TXB, RXB, DTRB#, DSRB #, RTSB#, CTSB#, CDB#, RIB# TXC, RXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC# TXD, RXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID# XTAL1 XTAL2 Data Bus Interface UART Channel B (same as Channel A) UART Channel C (same as Channel A) UART Channel D (same as Channel A) Crystal Osc/Buffer 564 BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XR16M564/564D 1.62V TO 3.63V www.DataSheet4U.com QUAD UART WITH 32-BYTE FIFO REV. 1.0.0 FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES INTSEL CDA# RIA# CDD# CDA# RID# GND VCC RXD RXA D7 D6 D5 D4 D3 D2 D1 D0 68 67 66 65 64 63 62 RID# GND RIA# RXA 68 67 66 65 64 63 62 63 9 8 7 6 5 4 3 2 1 DSRA# CTSA# DTRA# VCC RTSA# INTA CSA# TXA IOW# TXB CSB# INTB RTSB# GND DTRB# CTSB# DSRB# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 DSRD# CTSD# DTRD# GND RTSD# INTD CSD# TXD IOR# TXC CSC# INTC RTSC# VCC DTRC# CTSC# DSRC# DSRA# CTSA# DTRA# VCC RTSA# IRQ# CS# TXA R/W# TXB A3 N.C. RTSB# GND DTRB# CTSB# DSRB# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 63 9 8 7 6 5 4 3 2 1 CDD# GND VCC RXD D7 D6 D5 D4 D3 D2 D1 D0 60 59 58 57 56 55 DSRD# CTSD# DTRD# GND RTSD# N.C. N.C. TXD N.C. TXC A4 N.C. RTSC# VCC DTRC# CTSC# DSRC# XR16M564 68-pin PLCC Intel Mode (16/68# pin connected to VCC) 54 53 52 51 50 49 48 47 46 45 44 XR16M564 68-pin PLCC Motorola Mode (16/68# pin connected to GND) 54 53 52 51 50 49 48 47 46 45 44 16/68# TXRDY# CDB# CLKSEL RXRDY# RESET XTAL1 XTAL2 TXRDY# 16/68# CLKSEL RXRDY# RESET XTAL1 XTAL2 CDC# 60 56 54 52 64 62 61 59 57 55 51 58 53 50 DSRA# CTSA# DTRA# VCC RTSA# INTA CSA# TXA IOW# TXB CSB# INTB RTSB# GND DTRB# CTSB# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 29 23 22 25 26 27 28 30 31 17 20 18 19 24 32 63 49 CDD# CDA# GND RXD RID# RXA RIA# D6 D5 D4 D3 D1 D0 VCC D7 D2 48 47 46 45 44 43 DSRD# CTSD# DTRD# GND RTSD# INTD CSD# TXD IOR# TXC CSC# INTC RTSC# VCC DTRC# CTSC# XR16M564 64-pin TQFP Intel Mode Only 42 41 40 39 38 37 36 35 34 33 CLKSEL RIB# DSRB# CDB# CDC# RIC# A1 A0 RESET 2 DSRC# A2 XTAL1 XTAL2 RXB GND RXC CDC# CDB# RIC# RIB# RIC# RIB# GND RXB GND RXC RXC A2 A1 RXB A2 A1 A0 A0 XR16M564/564D REV. 1.0.0 www.DataSheet4U.com 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO FIGURE 3. PIN OUT ASSIGNMENT FOR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE 47 GND 38 INTSEL 46 D7 45 D6 44 D5 48 42 39 D0 37 VCC RXA 43 D4 41 D2.


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