Digital ADC. ADAS1128 Datasheet

ADAS1128 ADC. Datasheet pdf. Equivalent

Part ADAS1128
Description 24-bit Current To Digital ADC
Feature www.DataSheet4U.com 128 Channel, 24-bit Current to Digital ADC ADAS1128 GENERAL DESCRIPTION The ADA.
Manufacture Analog Devices
Datasheet
Download ADAS1128 Datasheet




ADAS1128
www.DataSheet4U.com
128 Channel, 24-bit Current to Digital ADC
Preliminary Technical Data
ADAS1128
FEATURES
128 Channel low level currents- to-digital converter
Up to 24 bit resolution
Up to 20ksps (50μs integration time)
Simultaneous Sampling
Ultra Low noise ( down to 0.4fC (2500e-) )
User adjustable full-scale range
INL: ±0.025% of Reading ±1ppm of FSR
Very Low Power dissipation: 4.5 mW/channel
LVDS/CMOS self-clocked serial interface
Daisy-chain Configuration registers
On-Board Temperature Sensor and Reference Buffer
Mini-BGA package 10mm × 10mm
Low-cost external components
APPLICATIONS
CT Scanner Data Acquisition
Photodiode Sensors and Power Monitoring
Spectroscopy
High Channel Count Data Acquisition Systems (current or
voltage input)
GENERAL DESCRIPTION
The ADAS1128 is a 128-Channel, current to digital analog-to-
digital converter ADC. It contains 128 low power, low noise,
low input current integrators, simultaneous sample-holds and
two high speed, high resolution ADCs with configurable
sampling rate and resolution up to 24 bits.
All converted channel results are output on a single LVDS self-
clocked serial interface reducing external hardware.
An SPI-compatible serial interface allows configuration of the
ADC using the SDI input. The SDO output allows one to daisy
chain several ADCs on a single, 3-wire bus. It uses the separate
supply VIO to reduce digital noise effect on the conversions.
The ADAS1128 is housed in a mini-BGA package, 10mm by
10mm.
SUPPORT TOOLS
Evaluation Board
Reference Design with reference layout (3 layers)
FPGA Verilog Code
FUNCTIONAL BLOCK DIAGRAM
BUFPL BUFNL
2.5V 3.3V
to next SDI
SDO
to all ADCs
AN0
AN63
AN64
AN127
KGND
F
OR0
S/H
F
OR63
F
S/H
S/H
OR64
F
S/H
OR127
VT
+
ADCL
-
REF
Configuration
SDI
OR(0:127)
Data Processing
LVDS/CMOS
Interface
+ ADCH
-
Temp
SDI
SCK
CS
RESET
DOUT
CLK
SYNC
IOVDD
IOGND
FPGA
2.5V
VIO
BUFPH BUFNH REF 2.048V
SDI
from previous
SDO
Figure 1. General Block Diagram
from DOUT
of other ADCs
For more information about the ADAS1128, contact Analog Devices, Inc., at adas@analog.com
Rev PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.



ADAS1128
ADAS1128www.DataSheet4U.com
Outline Dimensions
10.10
10.00 SQ
9.90
A1 BALL
INDICATOR
TOP VIEW
Preliminary Technical Data
*1.40
MAX
DETAIL A
SEATING
PLANE
DETAIL A
0.91 MIN
0.19 MIN
0.35
0.30
COPLANARITY
0.08
0.25
BALL DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-225
WITH EXCEPTION TO PACKAGE HEIGHT.
Figure 2 242-Ball Chip Scale Package Ball Grid Array [CSP-BGA]
(BC-242)
Dimensions shown in millimeters
Rev PrE | Page 2 of 3







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