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CY7C1416BV18 Dataheets PDF



Part Number CY7C1416BV18
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C14xxBV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
Datasheet CY7C1416BV18 DatasheetCY7C1416BV18 Datasheet (PDF)

www.DataSheet4U.com CY7C1416BV18, CY7C1427BV18 CY7C1418BV18, CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. .

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www.DataSheet4U.com CY7C1416BV18, CY7C1427BV18 CY7C1418BV18, CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1416BV18 and two 9-bit words in the case of CY7C1427BV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1416BV18 and CY7C1427BV18. On CY7C1418BV18 and CY7C1420BV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1418BV18 and two 36-bit words in the case of CY7C1420BV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 267 MHz clock for high bandwidth 2-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 534 MHz) at 267 MHz for DDR-II Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes DDR-II operates with 1.5 cycle read latency when DLL is enabled Operates as a DDR-I device with 1 cycle read latency in DLL off mode 1.8V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.4V–VDD) Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) Offered in both in Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Configurations CY7C1416BV18 – 4M x 8 CY7C1427BV18 – 4M x 9 CY7C1418BV18 – 2M x 18 CY7C1420BV18 – 1M x 36 Selection Guide Description Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 267 MHz 267 795 800 835 910 250 MHz 250 725 725 760 825 200 MHz 200 600 600 620 675 167 MHz 167 500 500 525 570 Unit MHz mA Cypress Semiconductor Corporation Document Number: 001-07033 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 27, 2007 [+] Feedback www.DataSheet4U.com CY7C1416BV18, CY7C1427BV18 CY7C1418BV18, CY7C1420BV18 Logic Block Diagram (CY7C1416BV18) A(20:0) LD K K DOFF 21 Write Add. Decode Read Add. Decode Address Register Write Reg 2M x 8 Array Write Reg 8 2M x 8 Array CLK Gen. Output Logic Control R/W C C CQ CQ 8 DQ[7:0] Read Data Reg. 16 8 Control Logic 8 Reg. Reg. Reg. 8 8 VREF R/W NWS[1:0] Logic Block Diagram (CY7C1427BV18) A(20:0) LD K K DOFF 21 Write Add. Decode Read Add. Decode Address Register Write Reg 2M x 9 Array Write Reg 9 2M x 9 Array CLK Gen. Output Logic Control R/W C C CQ CQ 9 DQ[8:0] Read Data Reg. 18 9 Control Logic 9 Reg. Reg. Reg. 9 9 VREF R/W BWS[0] Document Number: 001-07033 Rev. *C Page 2 of 29 [+] Feedback www.DataSheet4U.com CY7C1416BV18, CY7C1427BV18 CY7C1418BV18, CY7C1420BV18 Logic Block Diagram (CY7C1418BV18) A0 Burst Logic A(20:0) 21 LD K K 20 Write Add. Decode Read Add. Decode A(20:1) Address Register Write Reg 1M x 18 Array Write Reg 18 1M x 18 Array CLK Gen. Output Logic Control R/W C C CQ CQ 18 DQ[17:0] DOFF Read Data Reg. 36 18 Control Logic 18 Reg. Reg. Reg. 18 18 VREF R/W BWS[1:0] Logic Block Diagram (CY7C1420BV18) A0 Burst Logic A(19:0) 20 LD K K 19 Write Add. Decode Read Add. Decode A(19:1) Address Register Write Reg 512K x 36 Array Write Reg 512K x 36 Array 36 CLK Gen. Output Logic Control R/W C C CQ CQ 36 DQ[35:0] DOFF Read Data Reg. 72 36 Control Logic 36 Reg. Reg. Reg. 36 36 VREF R/W BWS[3:0] Document Number: 001-07033 Rev. *C Page 3 of 29 [+] Feedback www.DataSheet4U.com CY7C1416BV18, CY7C1427B.


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