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www.DataSheet4U.com
LPC3130/3131
Rev. 1.01 — 21 May 2009
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Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller
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Preliminary data sheet
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1. General description
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3130/3131 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.
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2. Features
2.1 Key features
CPU platform 180 MHz, 32-bit ARM926EJ-S 16 kB D-cache and 16 kB I-cache Memory Management Unit (MMU) Internal memory 96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM External memory interface NAND flash controller with 8-bit ECC 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM Communication and connectivity High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY Two I2S-bus interfaces Integrated master/slave SPI Two master/slave I2C-bus interfaces Fast UART Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA Four-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface System functions Dynamic clock gating and scaling Multiple power domains Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB DMA controller Four 32-bit timers
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NXP Semiconductors
www.DataSheet4U.com
LPC3130/3131
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Low-cost, low-power ARM926EJ-S microcontrollers
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Watchdog timer PWM module Random Number Generator (RNG) General Purpose I/O (GPIO) pins Flexible and versatile interrupt structure JTAG interface with boundary scan and ARM debug access Operating voltage and temperature Core voltage: 1.2 V I/O voltage: 1.8 V, 2.8 V, 3.3 V Temperature: −40 °C to +85 °C TFBGA180 package: 12 × 12 mm2, 0.8 mm pitch
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3. Ordering information
Table 1. Ordering information Package Name Description Version Type number
LPC3130FET180 TFBGA180 plastic thin fine pitch ball grid array package, 180 balls, body 12 × 12 × 0.8 mm SOT570-3 LPC3131FET180 TFBGA180 plastic thin fine pitch ball grid array package, 180 balls, body 12 × 12 × 0.8 mm SOT570-3 Table 2. Ordering options for LPC3130/3131 Core/bus frequency 180 MHz/ 90 MHz 180 MHz/ 90 MHz Total SRAM 96 kB High-speed USB Device/ Host/OTG 10-bit ADC channels 4 4 I2S-bus/ I2C-bus 2 each 2 each MCI SDHC/ Temperature SDIO/ range CE-ATA yes yes −40 °C to +85 °C −40 °C to +85 °C
Type number
LPC3130FET180 LPC3131FET180
192 kB Device/ Host/OTG
LPC3130_3131_1
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 21 May 2009
2 of 68
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NXP Semiconductors
www.DataSheet4U.com
LPC3130/3131
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Low-cost, low-power ARM926EJ-S microcontrollers
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4. Block diagram
JTAG interface
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TEST/DEBUG INTERFACE INSTRUCTION CACHE 16 kB DATA CACHE 16 kB
LPC3130/3131
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ARM926EJ-S
DMA CONTROLLER
USB 2.0 HIGH-SPEED OTG master slave slave ROM slave 96 kB ISRAM0 slave
master slave INTERRUPT CONTROLLLER slave master master
MPMC
slave
MULTILAYER AHB MATRIX slave
96 kB ISRAM1(1) NAND CONTROLLER BUFFER
slave MCI SD/SDIO slave AHB TO APB BRIDGE 0 ASYNC APB slave group 0 WDT SYSTEM CONTROL CGU slave AHB TO APB BRIDGE 1 ASYNC slave AHB TO APB BRIDGE 2 ASYNC slave AHB TO APB BRIDGE 3 ASYNC
slave AHB TO APB BRIDGE 4 SYNC APB slave group 4 NAND REGISTERS DMA REGISTERS
APB slave group 3 IOCONFIG I2S0/1 10-bit ADC EVENT ROUTER RANDOM NUMBER GENERATOR APB slave group 1 TIMER 0/1/2/3 PWM I2C0 I2C1
(1) LPC3131 only
APB slave group 2 UART LCD SPI PCM
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Fig 1.
LPC3130/3131 block diagram
LPC3130_3131_1
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 21 May 2009
3 of 68
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NXP Semiconductors
www.DataSheet4U.com
LPC3130/3131
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Low-cost, low-power ARM926EJ-S microcontrollers
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5. Pinning information
5.1 Pinning
ball A1 index area
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LPC3130/3131
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Transparent top view
Fig 2. Table 3. Row A 1 5 9 13 1 5 9 13 1 5 9 13 1 5 9 13
LPC3130/3131 pinning TFBGA1.