Audio Processor. ADAU1446 Datasheet

ADAU1446 Processor. Datasheet pdf. Equivalent

Part ADAU1446
Description (ADAU1445 / ADAU1446) Digital Audio Processor
Feature Data Sheet SigmaDSP Digital Audio Processor with Flexible Audio Routing Matrix ADAU1442/ADAU1445/AD.
Manufacture Analog Devices
Datasheet
Download ADAU1446 Datasheet




ADAU1446
Data Sheet
SigmaDSP Digital Audio Processor
with Flexible Audio Routing Matrix
ADAU1442/ADAU1445/ADAU1446
FEATURES
Fully programmable audio digital signal processor (DSP) for
enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz
4k parameter RAM, 8k data RAM
Flexible audio routing matrix (FARM)
24-channel digital input and output
Up to 8 stereo asynchronous sample rate converters
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)
Stereo S/PDIF input and output
Supports serial and TDM I/O, up to fS = 192 kHz
Multichannel byte-addressable TDM serial port
Pool of 170 ms digital audio delay (at 48 kHz)
Clock oscillator for generating master clock from crystal
PLL for generating core clock from common audio clocks
I2C and SPI control interfaces
Standalone operation
Self-boot from serial EEPROM
4-channel, 10-bit auxiliary control ADC
Multipurpose pins for digital controls and outputs
Easy implementation of available third-party algorithms
On-chip regulator for generating 1.8 V from 3.3 V supply
100-lead TQFP and LQFP packages
Temperature range: −40°C to +105°C
APPLICATIONS
Automotive audio processing
Head units
Navigation systems
Rear-seat entertainment systems
DSP amplifiers (sound system amplifiers)
Commercial audio processing
FUNCTIONAL BLOCK DIAGRAM
MP[3:0]/
SPI/I2C* SELFBOOT MP[11:4] ADC[3:0]
XTALI XTALO
ADAU1442/
ADAU1445/
ADAU1446
1.8V
REGULATOR
I2C/SPI CONTROL
INTERFACE
AND SELF-BOOT
MP/
AUX ADC
CLOCK
PLL OSCILLATOR
CLKOUT
SPDIFI
SDATA_IN[8:0]
(24-CHANNEL
DIGITAL AUDIO
INPUT)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
S/PDIF
RECEIVER
PROGRAMMABLE AUDIO
PROCESSOR CORE
S/PDIF
TRANSMITTER
FLEXIBLE AUDIO ROUTING MATRIX
(FARM)
SERIAL DATA
INPUT PORT
(×9)
UP TO 16 CHANNELS OF
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL DATA
OUTPUT PORT
(×9)
SERIAL CLOCK
DOMAINS
(×12)
SPDIFO
SDATA_OUT[8:0]
(24-CHANNEL
DIGITAL AUDIO
OUTPUT)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
*SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.
THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.
Figure 1.
Rev. D
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ADAU1446
ADAU1442/ADAU1445/ADAU1446
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
Digital Timing Specifications ..................................................... 8
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Theory of Operation ...................................................................... 17
System Block Diagram............................................................... 17
Overview...................................................................................... 18
Initialization ................................................................................ 20
Master Clock and PLL ............................................................... 21
Voltage Regulator ....................................................................... 25
SRC Group Delay ....................................................................... 25
Control Port ................................................................................ 26
Serial Data Input/Output........................................................... 31
Serial Input Ports ........................................................................ 37
Serial Input Port Modes and Settings ...................................... 39
Serial Output Ports..................................................................... 41
Serial Output Port Modes and Settings ................................... 42
Flexible Audio Routing Matrix (FARM) ................................. 46
Flexible Audio Routing Matrix Modes and Settings.............. 52
Asynchronous Sample Rate Converters .................................. 58
Data Sheet
ASRC Modes and Settings ........................................................ 58
DSP Core ..................................................................................... 60
DSP Core Modes and Settings.................................................. 61
Reliability Features ..................................................................... 62
RAMs ........................................................................................... 64
S/PDIF Receiver and Transmitter ............................................ 65
S/PDIF Modes and Settings ...................................................... 66
Multipurpose Pins...................................................................... 69
Multipurpose Pins Modes and Settings................................... 69
Auxiliary ADC............................................................................ 70
Auxiliary ADC Modes and Settings ........................................ 70
Interfacing with Other Devices .................................................... 71
Drive Strength Modes and Settings ......................................... 71
Flexible TDM Modes ..................................................................... 76
Serial Input Flexible TDM Interface Modes and Settings..... 76
Serial Output Flexible TDM Interface Modes and Settings . 78
Software Features............................................................................ 81
Software Safeload ....................................................................... 81
Software Slew .............................................................................. 81
Global RAM and Register Map .................................................... 82
Overview of Register Address Map ......................................... 82
Details of Register Address Map .............................................. 82
Applications Information .............................................................. 87
Layout Recommendations ........................................................ 87
Typical Application Schematics................................................ 89
Outline Dimensions ....................................................................... 92
Ordering Guide .......................................................................... 92
Rev. D | Page 2 of 92







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