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TC55VBM316AFTN Dataheets PDF



Part Number TC55VBM316AFTN
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet TC55VBM316AFTN DatasheetTC55VBM316AFTN Datasheet (PDF)

TC55VBM316AFTN/ASTN40,55 www.DataSheet4U.com TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provide.

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TC55VBM316AFTN/ASTN40,55 www.DataSheet4U.com TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 µA standby current (at VDD = 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package (TSOP). FEATURES • • • • • • • Low-power dissipation Operating: 9 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40° to 85°C Standby Current (maximum): 3.6 V 3.0 V 10 µA 5 µA • Access Times (maximum): TC55VBM316AFTN/ASTN 40 Access Time CE1 Access Time 55 55 ns 55 ns 55 ns 30 ns 40 ns 40 ns 40 ns 25 ns CE2 OE Access Time Access Time • Package: TSOP 48-P-1220-0.50 (AFTN) (Weight:0.51 g typ) TSOP 48-P-1214-0.50 (ASTN) (Weight:0.36 g typ) PIN ASSIGNMENT (TOP VIEW) 48 PIN TSOP PIN NAMES A0~A18 1 48 A-1~A18 CE1 , CE2 Address Inputs (Word Mode) Address Inputs (Byte Mode) Chip Enable Read/Write Control Output Enable Data Byte Control Data Inputs/Outputs Byte (×8 mode) Enable Power Ground No Connection Option R/W OE LB , UB 24 (Normal) 25 I/O1~I/O16 BYTE VDD GND NC OP* *: OP pin must be open or connected to GND. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 A15 17 A17 33 I/O3 2 A14 18 A7 34 I/O11 3 A13 19 A6 35 I/O4 4 A12 20 A5 36 I/O12 5 A11 21 A4 37 VDD 6 A10 22 A3 38 I/O5 7 A9 23 A2 39 8 A8 24 A1 40 9 NC 25 A0 41 10 NC 26 CE1 11 R/W 27 GND 43 12 CE2 28 OE 13 OP 29 I/O1 14 UB 15 LB 31 I/O2 16 A18 32 I/O10 48 A16 30 I/O9 42 44 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 45 46 47 I/O16 GND BYTE /A-1 2002-08-05 1/15 TC55VBM316AFTN/ASTN40,55 www.DataSheet4U.com BLOCK DIAGRAM CE A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A17 A18 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 VDD GND MEMORY CELL ARRAY 4,096 × 128 × 16 (8,388,608) ROW ADDRESS BUFFER ROW ADDRESS REGISTER ROW ADDRESS DECODER SENSE AMP DATA OUTPUT BUFFER CE A-1 A0 A1 A2 A3 A4 A5 A16 DATA INPUT BUFFER COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR CE1 CE2 LB CE UB R/W OE BYTE DATA OUTPUT BUFFER DATA INPUT BUFFER 2002-08-05 2/15 TC55VBM316AFTN/ASTN40,55 www.DataSheet4U.com OPERATING MODE MODE CE1 CE2 H H H H H H H H H H H H * L * OE R/W H H H H L L L L H H H H * * * BYTE L H H H L H H H L H H H H or L H or L H LB * L H L * L H L * L H L * * H UB I/O1~I/O8 Output Output High-Z Output Input Input High-Z Input High-Z High-Z High-Z High-Z High-Z High-Z High-Z I/O9~I/O15 High-Z Output Output High-Z High-Z Input Input High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z A-1 I/O16 POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS IDDS IDDS L Read L L L L Write L L L L Output Deselect L L L H Standby * * * = don't care H = logic high L = logic low L L L L * * * * H H H H * * * * L L H * L L H * L L H * * H Output Output High-Z A-1 Input Input High-Z A-1 High-Z High-Z High-Z High-Z High-Z High-Z MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE −0.3~4.2 −0.3*~4.2 −0.5~VDD + 0.5 0.6 260 −55~150 −40~85 UNIT V V V W °C °C °C *: −2.0 V when measured at a pulse width of 20ns DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) SYMBOL VDD VIH VIL VDH PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage VDD = 2.3 V~2.7 V VDD = 2.7 V~3.6 V MIN 2.3 2.0 2.2 −0.3* 1.5   VDD × 0.24 3.6 V V TYP   MAX 3.6 VDD + 0.3 UNIT V V *: −2.0 V when measured at a pulse width of 20ns 2002-08-05 3/15 TC55VBM316AFTN/ASTN40,55 www.DataSheet4U.com DC CHARACTERISTICS (Ta.


K3662 TC55VBM316AFTN SRB10100


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