Configurable GPIOs. CY8C20110 Datasheet

CY8C20110 GPIOs. Datasheet pdf. Equivalent

Part CY8C20110
Description Configurable GPIOs
Feature www.DataSheet4U.com CY8C20110 CapSense Express™-10 Configurable GPIOs with PWM Control Features ■ .
Manufacture Cypress Semiconductor
Datasheet
Download CY8C20110 Datasheet




CY8C20110
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CY8C20110
CapSense Express™-10 Configurable
GPIOs with PWM Control
Features
10 configurable IOs supporting
CapSenseTM buttons
LED drive
All GPIOs support LED dimming with configurable delay op-
tion
Interrupt outputs.
WAKE on interrupt input
Bi-directional sleep control pin
User defined input or output
2.4V to 3.6V and 4.75V to 5.25V operating voltage
Industrial temperature range: –40°C to +85°C
I2C slave interface for configuration and communication
I2C data transfer rate up to 400 kbps
Reduce BOM cost
Internal oscillator - no external oscillators or crystal
Free development tool - no external tuning components
Low operating current
Active current: continuous sensor scan: 1.5 mA
Deep sleep current: 4 uA
Available in 16-pin COL and 16-pin SOIC packages
Overview
The CapSense ExpressTM controller allows the control of 10 IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions.
The CY8C20110 is optimized for dimming LEDs in 15 selectable
duty cycles for back light applications. The device can be
configured to have up to 10 GPIOs connected to the PWM
output. The PWM duty cycle is programmable for variable LED
intensities.
The user has the ability to configure buttons, outputs, and param-
eters through specific commands sent to the I2C port. The IOs
have the flexibility of mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive, and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
Architecture
The logic block diagram illustrates the internal architecture of
CY8C20110.
The user is able to configure registers with parameters needed
to adjust the operation and sensitivity of the CapSense system.
CY8C20110 supports a standard I2C serial communication
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, along with sleep and watchdog timers.
System resources provide additional capability, such as a config-
urable I2C slave communication interface and various system
resets. The Analog system contains the CapSense PSoC block
which supports capacitive sensing of up to 10 inputs.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-17345 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 06, 2008
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CY8C20110
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Logic Block Diagram
External
Vcc
2.4 - 5.25V
10 Configurable IOs with
PWM Control
CapSense ExpressTM
Core
SYSTEM BUS
512B
SRAM
Interrupt
Controller
2KB Flash
Configuration and
Control Engine
Sleep and
Watchdog
Clock Sources
(Internal Main Oscillator)
SYSTEM BUS
CapSense
Block
Voltage and
I2C Current
Slave Reference
System
Resets
POR/
LVD
CY8C20110
Document Number: 001-17345 Rev. *E
Page 2 of 18
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