Configurable IOs. CY8C20140 Datasheet

CY8C20140 IOs. Datasheet pdf. Equivalent

Part CY8C20140
Description Configurable IOs
Feature CY8C20140 CapSense Express™ - 4 Configurable IOs Features ■ Overview The Cap.
Manufacture Cypress Semiconductor
Download CY8C20140 Datasheet

CapSense Express™ - 4 Configurable IOs
4 configurable IOs supporting
CapSense buttons
LED drive
Interrupt outputs
WAKE on interrupt input
User defined Input or output
2.4V to 5.25V operating voltage
Industrial temperature range: –40°C to +85°C
I2C slave interface for configuration
Reduce BOM cost
Internal oscillator - no external oscillators or crystal
Free development tool - no external tuning components
Low Operating Current
Active current: continuous sensor scan:1.5 mA
Sleep current: no scan, continuous sleep:2.6 uA
Available in 16-pin COL and 16-pin SOIC packages
The CapSense ExpressTM controller allows the control of 4 IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
The user has the ability to configure buttons, outputs, and
parameters, through specific commands sent to the I2C port. The
IOs have the flexibility in mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
The logic block diagram shows the internal architecture of
The user can configure registers with parameters needed to
adjust the operation and sensitivity of the CapSense system.
CY8C20140 supports a standard I2C serial communication
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, sleep, and watchdog timers. System
resources provide additional capability, such as a configurable
I2C slave communication interface and various system resets.
The Analog System is composed of the CapSense PSoC block
which supports capacitive sensing of up to 4 inputs.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-17348 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 11, 2008
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Logic Block Diagram
2.4 - 5.25V
CapSense ExpressTM
4 Configurable IOs
2KB Flash
Document Number: 001-17348 Rev. *C
Page 2 of 13
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