IBM0436A81BLAB Datasheet PDF


Part Number

IBM0436A81BLAB

Description

(IBM04xxAx1BLAB) 8Mb and 4Mb SRAM

Manufacture

IBM Corporation

Total Page 25 Pages
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Features Datasheet pdf . www.DataSheet4U.com Preliminary Feat ures IBM0418A81BLAB IBM0436A81BLAB IBM 0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM • 8Mb: 256K x 36 or 512K x 18 o rganizations 4Mb: 128K x 36 or 256K x 1 8 organizations • 0.25 Micron CMOS te chnology • Synchronous Pipeline Mode of Operation with Self-Timed Late Write • Single Differential HSTL Clock • +2.5V Power Supply, Ground, 1.5, 1.8V VDDQ, and 0.90V VREF • HSTL Input and Output levels • Registered Addresses , Write Enables, Synchronous Select, an d Data Ins • Registered Outputs • Common I/O • Asynchronous Output Enab le • Synchronous Power Down Input • Boundary Scan using limited set of JTAG 1149.1 functions • .
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IBM0436A81BLAB Datasheet
www.DataSheet4U.com
Preliminary
.
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25 Micron CMOS technology
• Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
• Single Differential HSTL Clock
• +2.5V Power Supply, Ground, 1.5, 1.8V VDDQ,
and 0.90V VREF
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Registered Outputs
• Common I/O
• Asynchronous Output Enable
• Synchronous Power Down Input
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability and Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4Mb and 8Mb SRAMs—IBM0436A41BLAB,
IBM0418A41BLAB, IBM0418A81BLAB, and
IBM0436A81BLAB—are Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, wide I/O, and
can achieve 3ns cycle times. Differential K clocks
are used to initiate the read/write operation and all
internal operations are self-timed. At the rising edge
of the K clock, all Addresses, Write-Enables, Sync
Select, and Data Ins are registered internally. Data
Outs are updated from output registers off the next
rising edge of the K clock. An internal Write buffer
allows write data to follow one cycle after addresses
and controls. The device is operated with a single
+2.5V power supply and is compatible with HSTL
I/O interfaces.
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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