Document
19-4467; Rev 0; 2/09
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+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs
General Description
The MAX3629 is a low-jitter precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications. Maxim’s proprietary PLL design features ultra-low jitter (0.4psRMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment. The MAX3629 contains five LVDS outputs and three LVCMOS outputs. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz by pin control. ♦ Crystal Oscillator Interface: 25MHz ♦ OSC_IN Interface: PLL Enabled: 25MHz PLL Disabled: 20MHz to 320MHz ♦ Outputs: One LVDS Output at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELA) Four LVDS Outputs at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELB) Three LVCMOS Outputs at 125MHz/156.25MHz (Selectable with FSELB) ♦ Low Phase Jitter: 0.4psRMS (12kHz to 20MHz) ♦ Excellent PSNR ♦ Operating Temperature Range: 0°C to +70°C
Features
MAX3629
Applications
Ethernet Networking Equipment
Typical Operating Circuit
+3.3V ±5%
Ordering Information
PART TEMP RANGE 0°C to +70°C PIN-PACKAGE 32 TQFN-EP* MAX3629CTJ+
10.5Ω
0.1μF
0.1μF
0.1μF
10μF VDDA 0.01μF
VDD
VDDO_DIFF
VDDO_SE Q0
Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
100Ω ASIC
Q0
Pin Configuration
VDDO_SE
OSC_IN MAX3629 33pF X_OUT 25MHz (CL = 18pF) X_IN 27pF
Q1
TOP VIEW
GND
Q7
Q6
Q2
24
100Ω ASIC
23
22
21
20
19
18
Q5
17 16 15 14 13 FSELB RESERVED Q4 Q4 VDDO_DIFF Q3 Q3 GND
Q2
VDDA 25 PLL_BP 26
100Ω ASIC
Q3 VDD PLL_BP Q3
VDD 27 FSELA 28 OSC_IN 29 MAX3629
GND 12 11 10 9 8 Q2
Q1
Q4
100Ω
ASIC
X_IN 30 X_OUT 31 GND 32
GND, OPEN, OR VDD
FSELA
Q4
VDDO_SE 6 VDDO_DIFF
100Ω
ASIC
RESERVED
+
1 Q0 2 Q0 3 GND 4 Q1 5 Q1
*EP
GND, OPEN, OR VDD
FSELB
33Ω Q5
125MHz/156.25MHz Z0 = 50Ω
ASIC
7 Q2
33Ω GND Q6
125MHz/156.25MHz Z0 = 50Ω
ASIC
33Ω Q7
125MHz/156.25MHz Z0 = 50Ω
THIN QFN-EP (5mm × 5mm)
ASIC
*EXPOSED PAD CONNECTED TO GROUND.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3629
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range at VDD, VDDA, VDDO_SE, VDDO_DIFF ................................................-0.3V to +4.0V Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q6, Q7, PLL_BP, FSELA, FSELB, OSC_IN .........................-0.3V to (VDD + 0.3V) Voltage Range at X_IN Pin ....................................-0.3V to +1.2V Voltage Range at X_OUT Pin ..........................-0.3V to (VDD - 0.6V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFN-EP (derate 34.5mW/°C above +70°C)..2759mW Operating Junction Temperature ......................-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1)
PARAMETER Power-Supply Current (Note 2) SYMBOL IDD PLL enabled PLL bypassed CONDITIONS MIN TYP 176 160 1.475 0.925 Figure 1 250 400 MAX 224 UNITS mA
LVDS OUTPUTS (Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4 Pins) Output High Voltage Output Low Voltage Differential Output Voltage Amplitude Change in Magnitude of Differential Output for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current Clock Output Rise/Fall Time Output Duty-Cycle Distortion LVCMOS/LVTTL OUTPUTS (Q5, Q6, Q7 Pins) Output High Voltage Output Low Voltage Output Rise/Fall Time Output Duty-Cycle Distortion Output Impedance R OUT VOH VOL tr, t f I OH = -12mA I OL = 12mA 20% to 80% at 125MHz (Note 5) PLL enabled, PLL bypassed (Note 4) 0.15 45 0.5 50 15 2.6 VDD 0.4 0.8 55 V V ns % tr, t f Shorted together Short to ground (Note .