Document
www.DataSheet4U.com
512K x 8 SRAM MODULE
SYS8512FKX-70/85/10/12
Issue 5.0: November 1999
Description
The SYS8512FKX is plastic 4M Static RAM Module housed in a standard 32 pin Dual-In-Line package organised as 512K x 8. The module utilises fast SRAMs housed in TSOP packages, and uses double sided surface mount techniques, buried decoder and dual board construction to achieve a very high density module. The module has Chip Select, Write Enable and Output Enable control inputs; the Output Enable pin allows faster access times than address access during a Read Cycle.
Features
• • • • • Access Times of 70/85/100/120 ns. Low seated height 32 Pin 0.6" Dual-In-Line package with JEDEC compatible pinout. 5 Volt Supply ± 10%. Low Power Dissipation: Average (min cycle) 605mW (maximum). Standby (CMOS) 44mW (maximum). Completely Static Operation. Equal Access and Cycle Times. All Inputs and Outputs Directly TTL Compatible. On-board Supply Decoupling Capacitors.
• • • •
Block Diagram
AO - A 16 D0 - D7
WE
Pin Definition
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS D7 D6 D5 D4 D3
OE 128K x 8 SRAM CS 128K x 8 SRAM CS 128K x 8 SRAM CS 128K x 8 SRAM CS
DECODER
Pin Functions
A17 CS A18
Address Inputs Data Input/Output Chip Select Input Read/Write Input Output Enable Input Power (+5V) Ground
PACKAGE TOP VIEW
A0 - A18 D0 - D7 CS WE OE VCC GND
ISSUE 5.0 November 1999
SYS8512FKX-70/85/10/12
www.DataSheet4U.com
DC OPERATING CONDITIONS Absolute Maximum Ratings (1)
Parameter
Voltage on any pin relative to VSS Power Dissipation Storage Temperature
Notes :
Symbol
VT PT TSTG
min
-0.3V -55
typ
1 -
max
+7 +150
unit
V W
o
C
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) Vt can be -3.5V pulse of less than 20ns.
Recommended Operating Conditions
Parameter
Supply Voltage Input High Voltage Input Low Voltage Operating Temperature
Symbol
VCC VIH VIL TA TAI
min
4.5 2.2 -0.3 0 -40
typ
5.0 -
max
5.5 Vcc + 0.3 0.8 70 85
unit
V V V
o o
C
C (I)
DC Electrical Characteristics (VCC=5V±10%)
TA 0 to 70OC min -
Parameter
Symbol Test Condition ILI1 ILO I CC TTL levels CMOS levels
0V - VIN - VCC CS = VIH, VI/O = GND to VCC CS = VIL ,II/O = 0mA, VIL - VIN - VCC-2.1V
typ(2) max Unit 16 70 24 5 0.2 10 ±8 ±8 45 110 40 12 8 500 µA µA mA mA mA mA mA µA
I/P Leakage Current A0~A16, OE Output Leakage Current D0~D7 Operating Supply Current Average Supply Current
I CC1 Min. Cycle, CS = VIL, VIN = VIL/VCC-2.1V I CC2 Min. Cycle, CS - 0.2V, VIN = 0.2V/VCC-0.2V ISB ISB1 ISB2
CS,A17-A18 = VCC-2.1V, VIL - VIN - VCC-2.1V CS,A17-A18 = VCC-0.2V, 0.2 - VIN - VCC-0.2V As above
Standby Supply Current
TTL levels CMOS levels -L Part
Output Voltage
VOL IOL = 2.1mA VOH IOH = -1.0mA
2.4
-
0.4 -
V V
Typical values are at VCC=5.0V,TA=25oC and specified loading.
2
SYS8512FKX-70/85/10/12 www.DataSheet4U.com
ISSUE 5.0 November 1999
Capacitance (VCC=5V±10%,TA=25oC)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance (CS, A17, A18) I/P Capacitance (other) I/O Capacitance Operation Truth Table
Symbol
CIN1 CIN2 CI/O
Test Condition
VIN = 0V VIN = 0V VI/O = 0V
max
10 40 40
Unit
pF pF pF
CS
H L L L
OE
X L L H
WE
X H L L
DATA PINS
High Impedance Data Out Data In Data In
SUPPLY CURRENT
ISB1 , ISB2 ICC1 , ICC2 ICC1 , ICC2 ICC1 , ICC2
MODE
Standby Read Write Write
Notes : H = VIH : L =VIL : X = VIH or VIL
Low Vcc Data Retention Characteristics - L Version Only
-L Part Parameter
VCC for Data Retention Data Retention Current
Symbol Test Condition
VDR
CS - VCC-0.2V VCC = 3.0V, CS = VCC-0.2V
min typ(1)
2.0 -
max
-
I CCDR2 I CCDR3 Chip Deselect to Data Retention Time Operation Recovery Time t CDR tR
TOP = 0C to 70C TOP = TAI
-
9 -
230 310
µA µA
-
See Retention Waveform See Retention Waveform
0 5
-
-
0 0
-
-
ns ms
Notes (1) Typical figures are measured at 25°C. (2) This parameter is guaranteed not tested.
AC Test Conditions * Input pulse levels: 0V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * VCC=5V±10%
Output Load
3
ISSUE 5.0 November 1999
SYS8512FKX-70/85/10/12
www.DataSheet4U.com
AC OPERATING CONDITIONS
Read Cycle
-70 Parameter
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to O/P in High Z
-85 min
85 10 10 5 0 0
-10 max
85 85 55 30 30
-12 max
-
Symbol min
t RC tAA tACS tOE t OH tCLZ tOLZ t CHZ 70 10 10 5 0 0
max
7.