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429 Transceiver. DEI1016 Datasheet

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429 Transceiver. DEI1016 Datasheet
















DEI1016 Transceiver. Datasheet pdf. Equivalent













Part

DEI1016

Description

Arinc 429 Transceiver



Feature


www.DataSheet4U.com Device Engineering Incorporated 385 East Alamo Drive Chan dler, AZ 85225 Phone: (480) 303-0822 Fa x: (480) 303-0824 E-mail: info@deiaz.co m DEI1016/DEI1016A/DEI1016B /DEI1016C ARINC 429 Transceiver Family • • • • • • • • Features Tw o Receivers and One Transmitter Industr y Standard Pin for Pin Replacement Part Wraparound Self-Test mode Word leng.
Manufacture

Device Engineering

Datasheet
Download DEI1016 Datasheet


Device Engineering DEI1016

DEI1016; th can be configured for 25 bit or 32 bi ts operation Parity Status and generati on of Receive and Transmit Words 8 Word Transmitter buffer Low Power CMOS proc essing Supports multiple ARINC protocol s: 429, 571, 575, 706 Available in exte nded (-55/+85°C) and Military (-55/+12 5°C) temperature ranges General Descr iption: The DEI1016 provides an interfa ce between a standar.


Device Engineering DEI1016

d avionics type serial digital data bus and a 16-bit-wide digital data bus. The interface circuit consists of a single channel transmitter with an 8X32 bit b uffer, two independent receive channels , and a host programmable control regis ter to select operating options. The tw o receiver channels operate identically , each providing a direct electrical in terface to an ARIN.


Device Engineering DEI1016

C data bus. The transmitter circuit cont ains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data into the tran smitter. The block of data is transmitt ed automatically by enabling the transm itter with no further attention by the host computer. Data is transmitted in T TL format on the D0(A)/D0(B) output pin s. The signal form.





Part

DEI1016

Description

Arinc 429 Transceiver



Feature


www.DataSheet4U.com Device Engineering Incorporated 385 East Alamo Drive Chan dler, AZ 85225 Phone: (480) 303-0822 Fa x: (480) 303-0824 E-mail: info@deiaz.co m DEI1016/DEI1016A/DEI1016B /DEI1016C ARINC 429 Transceiver Family • • • • • • • • Features Tw o Receivers and One Transmitter Industr y Standard Pin for Pin Replacement Part Wraparound Self-Test mode Word leng.
Manufacture

Device Engineering

Datasheet
Download DEI1016 Datasheet




 DEI1016
Device
www.DaEtaSnheegt4Ui.ncomeering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: info@deiaz.com
DEI1016/DEI1016A/DEI1016B
/DEI1016C ARINC 429
Transceiver Family
Features
Two Receivers and One Transmitter
Industry Standard Pin for Pin Replacement Part
Wraparound Self-Test mode
Word length can be configured for 25 bit or 32 bits operation
Parity Status and generation of Receive and Transmit Words
8 Word Transmitter buffer
Low Power CMOS processing
Supports multiple ARINC protocols: 429, 571, 575, 706
Available in extended (-55/+85°C) and Military (-55/+125°C) temperature ranges
General Description:
The DEI1016 provides an interface between a standard avionics type serial digital data bus and a 16-bit-wide digital data bus. The
interface circuit consists of a single channel transmitter with an 8X32 bit buffer, two independent receive channels, and a host
programmable control register to select operating options. The two receiver channels operate identically, each providing a direct
electrical interface to an ARINC data bus.
The transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data
into the transmitter. The block of data is transmitted automatically by enabling the transmitter with no further attention by the host
computer. Data is transmitted in TTL format on the D0(A)/D0(B) output pins. The signal format is compatible with DEI’s extensive
line of ARINC 429 Line drivers for easy connection to the ARINC data bus.
ARINC 429
Receive 0
ARINC 429
Receive 1
ARINC 429
Transmit
© 2005 Device Engineering Inc.
Receive
Decoder
Receive
Decoder
Transmit
Encoder
32
Control
Register
32
32
16
Host
Interface
32
TX FIFO
8 Words X 32 Bits
/DR1, /DR2
TXR
/OE1, /OE2
/LD1, /LD2
ENTX
/LDCW
/DBCEN
/MR
16 DATA BUS
Figure 1: DEI1016 Block Diagram
Page 1 of 17
DS-MW-01016-01 Rev A
01/07/2005




 DEI1016
Table 1: DEI 1016 Absolute Maximum Ratings
www.DataSheet4U.com
PARAMETER
SYMBOL
MIN
Supply Voltage
DC Input Voltage (except pins DI1(A,B) and DI2(A,B))
Voltage at pins DI1(A,B) and DI2(A,B)
Clamp diode current, any pin except DI inputs
VDD -0.5
VIN -0.6
VIN
DC Output Current per pin
DCV or GND current per pin
Storage Temperature
TSTG
-65
Junction Temperature, operating
TJmax
Lead Temperature (soldering, 10 sec)
TLead
1MCK Clock Frequency
MAX
+7.0
VCC + 0.6
±29
±25
±25
±50
+150
+145
+275
1.16
UNITS
V
V
V
mA
mA
mA
°C
°C
°C
MHz
Table 2: DEI 1016 DC Electrical Characteristics
Unless noted, operating conditions: VDD = 5V ± 10%, Extended Temp Devices: Ta = -55ºC to +85ºC, Military Temp Devices: Ta = -55ºC
to +125ºC
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ARINC LINE INPUTS
Logic 1 Input Voltage
Logic 0 Input Voltage
Null Input Voltage
Common Mode Voltage
VIH
VIL
VNUL
VCM
VDIFF DI(A) and DI(B)
VDIFF DI(A) and DI(B)
VDIFF DI(A) and DI(B)
6.5 10 13
-6.5 -10 -13
-2.5 0 +2.5
-5 +5
V
V
V
V
Differential Input Impedance
RI
12 k
Input Impedance to VDD
RH
12 k
Input Impedance to GND
RG
12 k
Differential Input Capacitance
Input Capacitance to VDD
Input Capacitance to GND
CI
CH
CG
LOGIC INPUTS (including bi-directional)
20 pF
20 pF
20 pF
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
VIL
VIH
IIN VIN = GND to VDD
0.8 V
2.0 V
-10 +10 µA
Input Capacitance
CIN
LOGIC OUTPUTS (including bi-directional)
15 pF
High Level Output Voltage
VOH IOH = 20µA (CMOS)
IOH = 6mA (TTL)
VDD – 0.1
2.7
V
Low Level Output Voltage
VOL IOL = 20µA (CMOS)
IOL = 6mA (TTL)
0.1 V
0.4
POWER SUPPLY INPUT
Supply Current
Supply Voltage
IDD 1MCK = 1MHz
VDD
5 10 mA
4.5 5 5.5 VDC
© 2005 Device Engineering Inc.
Page 2 of 17
DS-MW-01016-01 Rev A
01/07/2005




 DEI1016
Table 3: DEI 1016 AC Electrical Characteristics
www.DataSheet4U.com
PARAMETER
1MCK Frequency
1MCK Duty Cycle
1MCK Rise/Fall Time
Master Reset Pulse Width
Transmitter Data Rate (1MCK = 1MHz)
Receiver Data Rate (1MCK = 1MHz),(DATA = 50% BIT/
50% NULL TIME)
SYMBOL
f1MCK
CKDC
TCRF
TMR
TDR
RDR
Data Rate
100kbps
MIN
40
200
99
95
MAX
1.01
60
10
101
105
Data Rate
12.5kbps
MIN
40
200
12.4
8.0
MAX
1.01
60
10
12.6
14.5
UNITS
MHz
%
ns
ns
kbps
kbps
Table 4: Pin Definitions
SYMBOL
DEFINITION
VDD
GND
DI1(A)
DI1(B)
DI2(A)
DI2(B)
/DR1
/DR2
SEL
/OE1
/OE2
D[15:0]
/LD1
/LD2
TXR
DO(A)
DO(B)
ENTX
/LDCW
1MCK
TXCK
/MR
/DBCEN
Power Input. +5VDC ±10%
Power Return and Signal Ground.
ARINC 429 Input. Receiver Channel 1, “A” input
ARINC 429 Input. Receiver Channel 1, “B” input
ARINC 429 Input. Receiver Channel 2, “A” input
ARINC 429 Input. Receiver Channel 2, “B” input
Logic Output. Data Ready, Receiver 1. A Low output indicates valid data in receiver 1.
Logic Output. Data Ready, Receiver 2. A Low output indicates valid data in receiver 2.
Logic Input. Receiver word select. A Low input selects receiver Word 1; Hi selects Word 2 to be read on D[15:0] port.
Logic Input. Receiver 1 Output Enable. A Low input enables the D[15:0] port to output Receiver 1 data. Word 1 or
Word 2 will be output as determined by the SEL input.
Logic Input. Receiver 2 Output Enable. A Low input enables the D[15:0] port to output Receiver 2 data. Word 1 or
Word 2 will be output as determined by the SEL input.
Logic Input / Tri-state Output. This 16-bit bi-directional data port is the uP data interface. Receiver data is read from
this port. Control Register and Transmitter FIFO data is written into this port.
Logic Input. Load Transmitter Word 1. A Low input pulse loads Word 1 into the Transmitter FIFO from D[15:0].
Logic Input. Load Transmitter Word 2. A Low input pulse loads Word 2 into the Transmitter FIFO from D[15:0].
Logic Output. Transmitter Ready. A Hi output indicates the Transmitter FIFO is empty and ready to accept new data.
Logic Output. Transmitter serial data ‘A’ output. This is a return-to-zero format signal which will normally feed an
ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 1. The signal returns to zero for
second half of bit time.
Logic Output. Transmitter serial data ‘B’ output. This is a return-to-zero format signal which will normally feed an
ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 0. The signal returns to zero for
second half of bit time.
Logic Input. Enable Transmitter. A Hi input enables the Transmitter to send data from the Transmitter FIFO. This
must be Low while writing data into Transmitter FIFO. Transmitter memory is cleared by high-to-low transition.
Logic Input. Load Control Register. A Low input pulse loads the Control Register from D[15:0].
Logic Input. External Clock. Master clock used by both the Receivers and Transmitter. The 1MHz rate is a X10 clock
for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps).
Logic Output. Transmitter Clock. This outputs a clock frequency equal to the transmit data rate. The clock is always
enabled and in phase with the data. The output is Hi during the first half of the data bit time.
Logic Input. Master Reset. A Lo input resets the Transmitter FIFO, bit counters, word counter, gap timers, /DRx, and
TXR. The Control Register is not affected. Used on power up and system reset.
Logic Input with internal pull up to VDD. Data Bit Control Enable. A Low input enables the transmitter parity bit
control function as defined by control register bit 4 (PAREN). A Hi input forces transmitter parity bit insertion
regardless of PAREN value. The pin is normally left open or tied to ground.
© 2005 Device Engineering Inc.
Page 3 of 17
DS-MW-01016-01 Rev A
01/07/2005




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