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Silicon-Gate CMOS. KK4012B Datasheet

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Silicon-Gate CMOS. KK4012B Datasheet






KK4012B CMOS. Datasheet pdf. Equivalent




KK4012B CMOS. Datasheet pdf. Equivalent





Part

KK4012B

Description

Dual 4-Input NAND Gate High-Voltage Silicon-Gate CMOS



Feature


www.DataSheet4U.com TECHNICAL DATA KK4 012B Dual 4-Input NAND Gate High-Volta ge Silicon-Gate CMOS The KK4012B NAND g ates provide the system designer with d irect emplementation of the NAND functi on. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µ A at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • No ise margin (over full pack.
Manufacture

KODENSHI KOREA

Datasheet
Download KK4012B Datasheet


KODENSHI KOREA KK4012B

KK4012B; age temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMA TION KK4012BN Plastic KK4012BD SOIC TA = -55° to 125° C for all packages LO GIC DIAGRAM PIN ASSIGNMENT NC = NO CON NECTION PINS 6, 8 = NO CONNECTION PIN 14 =VCC PIN 7 = GND A L X X X H FUNCTI ON TABLE Inputs B X L X X H C X X L X H D X X X L H Output .


KODENSHI KOREA KK4012B

Y H H H H L X = don’t care 1 www.Da taSheet4U.com KK4012B MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Refere nced to GND) DC Input Voltage (Referenc ed to GND) DC Output Voltage (Reference d to GND) DC Input Current, per Pin Pow er Dissipation in Still Air, Plastic DI P+ SOIC Package+ Power Dissipation per Output Transistor St.


KODENSHI KOREA KK4012B

orage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0. 5 to VCC +0.5 -0.5 to VCC +0.5 ±10 750 500 100 -65 to +150 260 Unit V V V mA mW mW °C °C Maximum Ratings are tho se values beyond which damage to the de vice may occur. Functional operation sh ould be restricted to the Recommended O perating Conditions. .

Part

KK4012B

Description

Dual 4-Input NAND Gate High-Voltage Silicon-Gate CMOS



Feature


www.DataSheet4U.com TECHNICAL DATA KK4 012B Dual 4-Input NAND Gate High-Volta ge Silicon-Gate CMOS The KK4012B NAND g ates provide the system designer with d irect emplementation of the NAND functi on. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µ A at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • No ise margin (over full pack.
Manufacture

KODENSHI KOREA

Datasheet
Download KK4012B Datasheet




 KK4012B
www.DataSheet4U.com
Dual 4-Input NAND Gate
High-Voltage Silicon-Gate CMOS
TECHNICAL DATA
KK4012B
The KK4012B NAND gates provide the system designer with direct
emplementation of the NAND function.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4012BN Plastic
KK4012BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PINS 6, 8 = NO CONNECTION
PIN 14 =VCC
PIN 7 = GND
NC = NO CONNECTION
FUNCTION TABLE
Inputs
Output
A B CD
Y
L X XX
H
X L XX
H
X XLX
H
X XXL
H
H H HH
L
X = don’t care
1




 KK4012B
www.DataSheet4U.com
KK4012B
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC
VIN
VOUT
IIN
PD
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
750
500
PD Power Dissipation per Output Transistor
Tstg Storage Temperature
100
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC V
-55 +125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2




 KK4012B
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KK4012B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VIH Minimum High-Level VOUT=0.5 V or VCC - 0.5 V
Input Voltage
VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
VIL Maximum Low -
VOUT= VCC - 0.5V
Level Input Voltage VOUT= VCC - 1.0 V
VOUT= VCC - 1.5V
VOH Minimum High-Level VIN=GND or VCC
Output Voltage
VOL Maximum Low-Level VIN= VCC
Output Voltage
IIN Maximum Input
Leakage Current
VIN= GND or VCC
ICC Maximum Quiescent VIN= GND or VCC
Supply Current
(per Package)
IOL Minimum Output
VIN= GND or VCC
Low (Sink) Current UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
IOH Minimum Output
VIN= GND or VCC
High (Source) Current UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
VCC Guaranteed Limit
V -55°C 25 125 Unit
°C °C
5.0 3.5
10 7
15 11
3.5 3.5 V
77
11 11
5.0 1.5
10 3
15 4
1.5 1.5 V
33
44
5.0 4.95 4.95 4.95 V
10 9.95 9.95 9.95
15 14.95 14.95 14.95
5.0 0.05
10 0.05
15 0.05
0.05 0.05 V
0.05 0.05
0.05 0.05
18 ±0.1 ±0.1 ±1.0 µA
5.0 0.25
10 0.5
15 1.0
20 5.0
0.25 7.5 µA
0.5 15
1.0 30
5.0 150
5.0 0.64
10 1.6
15 4.2
mA
0.51 0.36
1.3 0.9
3.4 2.4
mA
5.0 -2.0 -1.6 -1.15
5.0 -0.64 -0.51 -0.36
10 -1.6 -1.3 -0.9
15 -4.2 -3.4 -2.4
3



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