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KK4042B Dataheets PDF



Part Number KK4042B
Manufacturers KODENSHI KOREA
Logo KODENSHI KOREA
Description High-Voltage Silicon-Gate CMOS
Datasheet KK4042B DatasheetKK4042B Datasheet (PDF)

www.DataSheet4U.com TECHNICAL DATA KK4042B Quad Clocked «D» Latch High-Voltage Silicon-Gate CMOS KK4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input. For POLARITY =.

  KK4042B   KK4042B


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www.DataSheet4U.com TECHNICAL DATA KK4042B Quad Clocked «D» Latch High-Voltage Silicon-Gate CMOS KK4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARTY = 1) the information present at the input during the CLOCK transition is retained at the outputs until an opposite CLOCK transition occurs. The KK4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes); 16-lead dual-in-line plastic package (E suffix), and in chip form (H suffix). • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION KK4042BN Plastic KK4042BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Clock 0 1 1 0 PIN 16 =VCC PIN 8 = GND Polarity 0 0 1 1 Outputs Q D Latch D Latch 1 www.DataSheet4U.com KK4042B MAXIMUM RATINGS* Symbol VCC VI VOUT II PD Ptot Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±10 750 500 100 -65 to +150 260 Unit V V V mA mW mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 www.DataSheet4U.com KK4042B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VСС Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit ≥-55°C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±0.1 1 2 4 20 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25°C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±0.1 1 2 4 20 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 ≤125 °C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±1.0 30 60 120 600 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V VIL V VOH V VOL VIN=GND or VCC V IIN IСС VIN= GND or VCC VIN= GND or VCC µA µA IOL VIN= GND or VCC VOL=0.4 V VOL=0.5 V VOL=1.5 V mA IOH Minimum Output VIN= GND or VCC High (Source) Current VOH=2.5 V VOH=4.6 V VOH=9.5 V VOH=13.5 V 3 www.DataSheet4U.com KK4042B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200 kΩ, Input tr=tf=20 ns) VCC Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Clock to Q (Figure 1) Maximum Propagation Delay, Clock to Q (Figure 1) Maximum Propagation Delay, Data to Q (Figure 2) Maximum Propagation Delay, Data to Q (Figure 2) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 450 200 160 500 230 180 220 110 80 300 150 100 200 100 80 Guaranteed Limit ≥-55°C 25°C 450 200 160 500 230 180 220 110 80 300 150 100 200 100 80 7.5 ≤125°C 900 400 320 1000 460 3.


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