LED Driver. NCP5021 Datasheet

NCP5021 Driver. Datasheet pdf. Equivalent

Part NCP5021
Description High Voltage White LED Driver
Feature NCP5021 High Voltage White LED Driver with Ambient Light Sensing The NCP5021 product is a single ou.
Manufacture ON Semiconductor
Datasheet
Download NCP5021 Datasheet




NCP5021
NCP5021
High Voltage White LED
Driver with Ambient Light
Sensing
The NCP5021 product is a single output boost LED driver capable
of driving up to 8 LEDs in series for portable backlight applications.
The builtin DC/DC converter is based on a high efficient PWM
boost structure with 32 V output voltage span. It provides a peak 90%
efficiency together with a 1% ILED current tolerance.
Features
2.7 to 5.5 V Input Voltage Range
90% Peak efficiency with 4.7 mH / 150 mW Inductor
Gradual Dimming Builtin (Automatic Fade In/Fade Out Effect)
Integrated Ambient Light Sensing Automatically Adjusts the LCD
Backlight Contrast
Builtin Zero Current Load Leakage under Idle Mode
Support the Full I2C Protocol with Address Extension
Tight 1% ILED Tolerance
Ultra Thin 0.5 mm QFN16 Package
This is a PbFree Device
Typical Applications
Cellular Phone, Smartphone
Portable Media Player (PMP)
Global Positioning System (GPS)
+Vbat
L1
NSR0240M2T5G
GND C1
4.7mH
D8
4.7mF/6.3V 15 Vbat
Lx 13
SCL
SDA
1 SCL
2 SDA
Vos 16 R3
470R
GND
SFH5711 U3
Log
4
C3
100nF
R3
3 I2CADR
4 VSB
U1
R4 22k GND
NCP5021
C2
GND
12
220k
5 AMBS
C4
GND
R1 2.2mH 7 IREF
12k R2 6 IPK
NNNCCC
22k GND GND FB 9
8 14
1112
10
D1
D2
D3
D4
D5
D6
D7
D8
GND
Figure 1. Typical Large Display LED Driver
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UQFN16
MU SUFFIX
CASE 523AF
MARKING DIAGRAM
5021
ALYWG
G
5021
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
SCL
SDA
I2CADR
VSB
NC
NC
NC
FB
(Top View)
NC = Not Connected
ORDERING INFORMATION
Device
Package
Shipping
NCP5021MUTXG UQFN16 3000 / Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
July, 2010 Rev. 1
1
Publication Order Number:
NCP5021/D



NCP5021
NCP5021
Table 1. PIN DESCRIPTIONS
PIN Name
Type
Description
1 SCL
INPUT,
DIGITAL
This pin carries the I2C clock to control the DC/DC converter and to set up the output current and
the photo sensor. The SCL clock is associated with the SDA signal.
2 SDA
INPUT,
DIGITAL
This pin carries the data provided by the I2C protocol. The content of the SDA byte is used to pro-
gram the mode of operation and to set up the output current.
3 I2CADR
INPUT,
DIGITAL
This pin is used to select the I2C address of the NCP5021:
I2CADR = Low ³ address = %0111 0010 = $72
I2CADR = High ³ address = %0111 0100 = $74
In order to avoid any risk during the operation, the digital levels are intended to be hardwired prior to
power up the system.
4 VSB
POWER,
OUTPUT
This pin provides a switched voltage, derived from the Vbat supply, to bias the external photo sense.
The current capability of this voltage is 1 mA.
The VSB pin is disconnected when the Shutdown mode has been engaged.
5 AMBS
INPUT,
This pin senses the voltage developed across the external Photo Bias resistor. Since this is a very
ANALOG high impedance input, cares must be observed to minimize the leakage current and the noise that
may influence the photo sense analog function. The bias parameters associated with the AMBS pin
are reloaded when the chip resumes from Shutdown to Normal operation.
6 IPK
INPUT,
This pin provides the inductor peak current during normal operation. In no case shall the voltage at
ANALOG IPK pin be forced either higher or lower than the 1144 mV provided by the internal reference.
7 IREF
INPUT,
This pin provides the reference current, based on the internal bandgap voltage reference, to con-
ANALOG trol the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the
highest accuracy of the LED biases. An external current source can be used to bias this pin to dim
the light coming out of the LED.
In no case shall the voltage at IREF pin be forced either higher or lower than the 1144 mV provided
by the internal reference.
8 AGND
POWER
This pin is the GROUND signal for the analog and digital blocks and must be connected to the sys-
tem ground. A ground plane is strongly recommended.
9 FB
INPUT,
ANALOG
This pin is the current sense of the series arranged LED. The builtin current mirror will automatic-
ally adapt the voltage drop across this pin (typically 400 mV).
10 NC
This pin shall be left open for normal operation.
11 NC
This pin shall be left open for normal operation.
12 NC
This pin shall be left open for normal operation.
13 Lx
POWER
The external inductor shall be connected between this pin (drain of the internal Power switch) and
Vbat. The voltage is internally clamped at 40 V under worst case conditions. The external Schottky
diode shall be connected as close as possible to this pin. See Note 1 for ESR recommendations.
14 PGND
POWER
This pin is the GROUND reference for the DC/DC converter and the output current control. The pin
must be connected to the system ground, a ground plane being strongly recommended.
15 VBAT
INPUT,
POWER
Input Battery voltage to supply the analog , the digital blocks and the main Power switch driver. The
pin must be decoupled to ground by a 10 mF ceramic capacitor.
16 Vos
OUTPUT,
POWER
This pin senses the output voltage supplied by the DC/DC converter. The Vos pin must be by-
passed by 1.0 mF/50 V ceramic capacitor located as close as possible to the pin to properly bypass
the output voltage to ground. The circuit shall not operate without such bypass capacitor connected
to the Vos pin.
The output voltage is internally clamped to 40 V maximum in the event of no load situation.
NOTE: Due to the very fast dV/dt transient developed during the operation, using a low pass filter is
strongly recommended as depicted in the schematic diagram Figure 1.
NC
Not Back side exposed pad is not internally connected and can be either left floating or connected to the
Connected system Ground.
1. Using low ESR ceramic capacitor (X5R or better) and low ESR inductor with minimum Eddie losses is mandatory to optimize the DC/DC
efficiency.
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