DELAY LINE. 3D7105 Datasheet

3D7105 LINE. Datasheet pdf. Equivalent

Part 3D7105
Description MONOLITHIC 5-TAP FIXED DELAY LINE
Feature 3D7105 www.DataSheet4U.com MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105) FEATURES • • • • • • •.
Manufacture Data Delay Devices
Datasheet
Download 3D7105 Datasheet




3D7105
MONOLITHIC 5-TAPwww.DataSheet4U.com
FIXED DELAY LINE
(SERIES 3D7105)
3D7105
data
delay
3
®
devices, inc.
FEATURES
PACKAGES
All-silicon, low-power CMOS IN
technology
O2
O4
TTL/CMOS compatible
GND
18
27
36
45
VDD
O1
O3
O5
IN
O2
inputs and outputs
3D7105Z
O4
Vapor phase, IR and wave
SOIC
GND
1
2
3
4
8 VDD
7 O1
6 O3
5 O5
solderable
Auto-insertable (DIP pkg.)
(150 Mil)
3D7105M DIP
3D7105H Gull-Wing
Low ground bounce noise
(300 Mil)
Leading- and trailing-edge accuracy
Delay range: .75 through 80ns
Delay tolerance: 5% or 1ns
Temperature stability: ±3% typical (0C-70C)
Vdd stability: ±1% typical (4.75V-5.25V)
Minimum input pulse width: 30% of total delay
IN
N/C
N/C
O2
N/C
O4
N/C
GND
1
2
3
4
5
6
7
8
16 VDD
15 N/C
14 N/C
13 O1
12 N/C
11 O3
10 N/C
9 O5
14-pin DIP and 16-pin SOIC available as drop-in
replacements for hybrid delay lines
3D7105S SOIC
(300 Mil)
IN
N/C
N/C
O2
N/C
O4
GND
1 14 VDD
2 13 N/C
3 12 O1
4 11 N/C
5 10 O3
6 9 N/C
7 8 O5
3D7105 DIP
3D7105G Gull-Wing
3D7105K Unused pins
removed
(300 Mil)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7105 5-Tap Delay Line product family consists of fixed-delay
IN Delay Line Input
CMOS integrated circuits. Each package contains a single delay line,
O1 Tap 1 Output (20%)
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
O2 Tap 2 Output (40%)
(incremental) delay values can range from 0.75ns through 8.0ns. The
O3 Tap 3 Output (60%)
input is reproduced at the outputs without inversion, shifted in time as per O4 Tap 4 Output (80%)
the user-specified dash number. The 3D7105 is TTL- and CMOS-
O5 Tap 5 Output (100%)
compatible, capable of driving ten 74LS-type loads, and features both
VCC +5 Volts
rising- and falling-edge accuracy.
GND Ground
N/C No Connection
The all-CMOS 3D7105 integrated circuit has been designed as a reliable,
economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP
and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
TOLERANCES
DIP-8
SOIC-8 DIP-14 SOIC-16
TOTAL
TAP-TAP
Max
3D7105M 3D7105Z 3D7105 3D7105S DELAY (ns)
DELAY
Operating
3D7105H
3D7105G
(ns) Frequency
3D7105K
-.75 -.75 -.75 -.75 3.0 ± 1.0* 0.75 ± 0.4 41.7 MHz
-1
-1
-1
-1
4.0 ± 1.0* 1.0 ± 0.5
37.0 MHz
-1.5 -1.5 -1.5 -1.5 6.0 ± 1.0* 1.5 ± 0.7 30.3 MHz
-2
-2
-2
-2
8.0 ± 1.0* 2.0 ± 0.8
25.6 MHz
-2.5
-2.5
-2.5
-2.5 10.0 ± 1.0* 2.5 ± 1.0
22.2 MHz
-4
-4
-4
-4 16.0 ± 1.0* 4.0 ± 1.3
15.9 MHz
-5 -5 -5 -5 25.0 ± 1.3 5.0 ± 1.5 13.3 MHz
-8 -8 -8 -8 40.0 ± 2.0 8.0 ± 1.5 9.52 MHz
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns
NOTE: Any dash number between .75 and 8 not shown is also available.
INPUT RESTRICTIONS
Absolute
Min
Max
Operating
Oper. Freq. Pulse Width
Absolute
Min
Oper. P.W.
166.7 MHz
166.7 MHz
166.7 MHz
166.7 MHz
133.3 MHz
83.3 MHz
66.7 MHz
41.7 MHz
12.0 ns
13.5 ns
16.5 ns
19.5 ns
22.5 ns
31.5 ns
37.5 ns
52.5 ns
3.00 ns
3.00 ns
3.00 ns
3.00 ns
3.75 ns
6.00 ns
7.50 ns
12.0 ns
©1996 Data Delay Devices
Doc #96006
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1



3D7105
3D7105
www.DataSheet4U.com
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7105 five-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and
supply voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7105 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended
that the engineering staff at DATA DELAY
DEVICES be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7105 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
IN O1 O2 O3 O4 O5
IN O1 O2 O3 O4 O5
25% 25% 25% 25%
20% 20% 20% 20% 20%
Temp & VDD
Compensation
Temp & VDD
Compensation
VDD
Dash numbers < 5
GND
VDD
Dash numbers >= 5
Figure 1: 3D7105 Functional Diagram
Doc #96006
DATA DELAY DEVICES, INC.
12/2/96
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
GND
2







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