DELAY LINE. 3D7110 Datasheet

3D7110 LINE. Datasheet pdf. Equivalent

Part 3D7110
Description MONOLITHIC 10-TAP FIXED DELAY LINE
Feature 3D7110 www.DataSheet4U.com MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110) FEATURES PACKAGES IN .
Manufacture Data Delay Devices
Datasheet
Download 3D7110 Datasheet




3D7110
MONOLITHICwww.DataSheet4U.com 10-TAP
FIXED DELAY LINE
(SERIES 3D7110)
3D7110
FEATURES
PACKAGES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
IN 1
N/C 2
O2 3
14 VDD
13 O1
12 O3
IN 1 14 VDD
N/C 2 13 O1
O2 3 12 O3
O4 4 11 O5
O6 5 10 O7
O8 6 9 O9
Low ground bounce noise
O4 4 11 O5
GND 7 8 O10
Leading- and trailing-edge accuracy
Delay range: .75 through 80ns
O6 5
O8 6
10 O7
9 O9
3D7110D SOIC
(150 Mil)
Delay tolerance: 5% or 1ns
Temperature stability: ±3% typical (0C-70C)
Vdd stability: ±1% typical (4.75V-5.25V)
Minimum input pulse width: 15% of total delay
GND 7
8 O10
3D7110 DIP
3D7110G Gull-Wing
IN 1
N/C 2
N/C 3
O2 4
16 VDD
15 N/C
14 O1
13 O3
14-pin Gull-Wing and 16-pin SOIC
available as drop-in replacements
for hybrid delay lines
For mechanical dimensions, click here.
For package marking details, click here.
O4
O6
O8
GND
5
6
7
8
12 O5
11 O7
10 O9
9 O10
3D7110S SOL
(300 Mil)
FUNCTIONAL DESCRIPTION
The 3D7110 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 8.0ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7110 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D7110 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is offered
in a standard 14-pin auto-insertable DIP and space saving surface
mount 14- and 16-pin SOIC packages.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
VDD
GND
Delay Line Input
Tap 1 Output (10%)
Tap 2 Output (20%)
Tap 3 Output (30%)
Tap 4 Output (40%)
Tap 5 Output (50%)
Tap 6 Output (60%)
Tap 7 Output (70%)
Tap 8 Output (80%)
Tap 9 Output (90%)
Tap 10 Output (100%)
+5 Volts
Ground
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1



3D7110
3D7110
www.DataSheet4U.com
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DIP-14 SOIC-14 SOIC-16
3D7110 3D7110D 3D7110S
3D7110G
-.75 -.75 -.75
-1 -1 -1
-1.5 -1.5 -1.5
-2 -2 -2
-2.5 -2.5 -2.5
-4 -4 -4
-5 -5 -5
-8 -8 -8
TOLERANCES
TOTAL
TAP-TAP
DELAY
DELAY
(ns) (ns)
6.75 ± 1.0* 0.75 ± 0.4
9.0 ± 1.0* 1.0 ± 0.5
13.5 ± 1.0* 1.5 ± 0.7
18.0 ± 1.0* 2.0 ± 0.8
22.5 ± 1.1* 2.5 ± 1.0
36.0 ± 1.8* 4.0 ± 1.3
50.0 ± 2.5 5.0 ± 1.5
80.0 ± 4.0 8.0 ± 1.5
Max
Operating
Frequency
28.4 MHz
23.8 MHz
18.0 MHz
14.5 MHz
18.2 MHz
8.33 MHz
6.67 MHz
4.17 MHz
INPUT RESTRICTIONS
Absolute
Min
Max Operating
Oper. Freq. Pulse Width
166.7 MHz
17.6 ns
166.7 MHz
21.0 ns
166.7 MHz
27.8 ns
166.7 MHz
34.5 ns
125.0 MHz
27.5 ns
133.3 MHz
60.0 ns
66.7 MHz
75.0 ns
41.7 MHz
120.0 ns
Absolute
Min
Oper. P.W.
3.00 ns
3.00 ns
3.00 ns
3.00 ns
4.00 ns
6.00 ns
7.50 ns
12.0 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns
NOTE: Any dash number between .75 and 8 not shown is also available.
1996 Data Delay Devices
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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