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STK32N4LLF5
N-channel 40 V, 0.0017 Ω, 32 A, PolarPAK® STripFET™ V Power MOSFET
Preliminary Data
Features
Type STK32N4LLF5
■ ■ ■ ■ ■ ■ ■
VDSS RDS(on) max RDS(on)*Qg 40 V < 0.0025 Ω 106.4nC*mΩ
Ultra low top and bottom junction to case thermal resistance Extremely low on-resistance RDS(on) RDS(on)*Qg industry benchmark High avalanche ruggedness Fully encapsulated die 100% Matte tin finish (in compliance with the 2002/95/EC european directive) PolarPAK® is a trademark of VISHAY Figure 1. Internal schematic diagram
PolarPAK®
Application
■
Switching applications
Description
This product utilizes the 5th generation of design rules of ST’s proprietary STripFET™ technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved.
Bottom View
Top View
Table 1.
Device summary
Order code Marking 324L5 Package PolarPAK® Packaging Tape and reel
STK32N4LLF5
January 2009
Rev 1
1/12
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Contents
STK32N4LLF5
Contents
1 2 3 4 5 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuits .............................................. 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STK32N4LLF5
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C Derating factor Value 40 ± 22 32 20 128 5.2 0.0416 TBD -55 to 150 Unit V V A A A W W/°C J °C
ID IDM
(2) (1)
PTOT
EAS (3) TJ Tstg
Single pulse avalanche energy Operating junction temperature Storage temperature
1. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and ≤ 10sec 2. Pulse width limited by package 3. Starting TJ = 25 °C, ID = 16 A, VDD = 25 V
Table 3.
Symbol
Thermal data
Parameter Typ. 20 0.8 2.2 Max. 24 1 2.7 Unit °C/W °C/W °C/W
Rthj-amb(1) Thermal resistance junction-amb Rthj-c
(2)
Thermal resistance junction-case (top drain) Thermal resistance junction-case (source)
1inch2, 2 oz. Cu. and ≤ 10sec
Rthj-c(3)
1. When mounted on FR-4 board of 2. Steady State
3. Measured at Source pin when the device is mounted on FR-4 board in steady state
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Electrical characteristics
STK32N4LLF5
2
Electrical characteristics
(TCASE = 25 °C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 µA, VGS= 0 VDS = Max rating, VDS = Max rating,Tc=125°C VGS = ± 22 V VDS= VGS, ID = 250 µA VGS= 10 V, ID= 16 A VGS= 4.5 V, ID= 16 A 1 Min. 40 1 10
±100
Typ.
Max.
Unit V µA µA nA V Ω Ω
2.5 0.0017 0.0025 0.0022 0.0030
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Gate input resistance Test conditions Min. Typ. 4900 646 100 38 TBD TBD TBD Max. Unit pF pF pF nC nC nC Ω
VDS =25 V, f=1 MHz, VGS=0
VDD=15 V, ID = 32 A VGS =4.5 V (see Figure 3) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain
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STK32N4LLF5
Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 15 V, ID= 16 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) Min. Typ. TBD TBD TBD TBD Max. Unit ns ns ns ns
Table 7.
Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 16 A, VGS=0 ISD= 32 A, di/dt = 100 A/µs, VDD=20 V, TJ=150 °C (see Figure 7) TBD TBD TBD Test conditions Min. Typ. Max. 32 128 1.1 Unit A A V ns nC A
1. Pulse width limited by package 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Test circuits
STK32N4LLF5
3
Figure 2.
Test circuits
Switching times test circuit for resistive load Figure 3. Gate charge test circuit
Figure 4.
Test circuit for inductive load Figure 5. switching and diode recovery times
Unclamped inductive load test circuit
Figure 6.
Unclamped inductive .