PO74HSTL85350A

www.DataSheet4U.com PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 300MHz HSTL Potato Chip 03/24/07 FEATURES: . Patented Technology . Four HSTL differential outputs . Two single LVTTL/LVCMOS inputs . Operating frequency up to 300MHz with 15 pf load . Very low output pin to pin skew < 50ps . 3.4-ns propagation delay (max) . 2.4V to 3.6V power supply . Industrial temperature range: –40°C to 85°C . 20-pin TSSOP package DESCRIPTION: The PO74HSTL85350A is a low-skew, 1-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on CMOS technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 300MHz . The device features two single-ended input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The PO74HSTL85350A functions as a signal-level translator and fanout on LVCMOS / LVTTL single-ended signal to four HSTL differential loads. Since the PO74HSTL85350A introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Pin Configuration VEE CLK_EN CLK_SEL CLK0 nc CLK1 nc nc nc VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Logic Block Diagram Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 CLK_EN D Q LE CLK0 CLK1 0 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q2...