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Low-power buffer. 74AUP1G07 Datasheet

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Low-power buffer. 74AUP1G07 Datasheet






74AUP1G07 buffer. Datasheet pdf. Equivalent




74AUP1G07 buffer. Datasheet pdf. Equivalent





Part

74AUP1G07

Description

Low-power buffer



Feature


www.DataSheet4U.com 74AUP1G07 Low-power buffer with open-drain output Rev. 02 — 14 June 2007 Product data sheet 1. General description The 74AUP1G07 is a high-performance, low-power, low-volta ge, Si-gate CMOS device, superior to mo st advanced CMOS compatible TTL familie s. Schmitt trigger action at all inputs makes the circuit tolerant to slower i nput rise and fall t.
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP1G07 Datasheet


NXP Semiconductors 74AUP1G07

74AUP1G07; imes across the entire VCC range from 0. 8 V to 3.6 V. This device ensures a ver y low static and dynamic power consumpt ion across the entire VCC range from 0. 8 V to 3.6 V. This device is fully spec ified for partial Power-down applicati ons using IOFF. The IOFF circuitry disa bles the output, preventing the damagin g backflow current through the device when it is powered dow.


NXP Semiconductors 74AUP1G07

n. The 74AUP1G07 provides the single non -inverting buffer with open-drain outpu t. The output of the device is an open drain and can be connected to other ope n-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND func tions. 2. Features s Wide supply volta ge range from 0.8 V to 3.6 V s High noi se immunity s Complies with JEDEC stand ards: x JESD8-12 (.


NXP Semiconductors 74AUP1G07

0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.6 5 V) x JESD8-7 (1.2 V to 1.95 V) x JESD 8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V t o 3.6 V) s ESD protection: x HBM JESD22 -A114E Class 3A exceeds 5000 V x MM JES D22-A115-A exceeds 200 V x CDM JESD22-C 101C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s.

Part

74AUP1G07

Description

Low-power buffer



Feature


www.DataSheet4U.com 74AUP1G07 Low-power buffer with open-drain output Rev. 02 — 14 June 2007 Product data sheet 1. General description The 74AUP1G07 is a high-performance, low-power, low-volta ge, Si-gate CMOS device, superior to mo st advanced CMOS compatible TTL familie s. Schmitt trigger action at all inputs makes the circuit tolerant to slower i nput rise and fall t.
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP1G07 Datasheet




 74AUP1G07
www.DataSheet4U.com
74AUP1G07
Low-power buffer with open-drain output
Rev. 02 — 14 June 2007
Product data sheet
1. General description
The 74AUP1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G07 provides the single non-inverting buffer with open-drain output. The
output of the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114E Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C




 74AUP1G07
www.DNatXaSPheSete4Um.coicmonductors
74AUP1G07
Low-power buffer with open-drain output
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1G07GW 40 °C to +125 °C TSSOP5
74AUP1G07GM 40 °C to +125 °C XSON6
74AUP1G07GF 40 °C to +125 °C XSON6
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP1G07GW
74AUP1G07GM
74AUP1G07GF
5. Functional diagram
Marking code
pS
pS
pS
2A
Y4
mna623
Fig 1. Logic symbol
A2
4Y
mna624
Fig 2. IEC logic symbol
Y
A
GND
mna625
Fig 3. Logic diagram
74AUP1G07_2
Product data sheet
Rev. 02 — 14 June 2007
© NXP B.V. 2007. All rights reserved.
2 of 16




 74AUP1G07
74AUP1G07w NXwP Semw icon.ductoDrs a t a S h e e t 4 U . c o m
Low-power buffer with open-drain output
6. Pinning information
6.1 Pinning
74AUP1G07
74AUP1G07
n.c. 1
6 VCC
n.c. 1
A2
GND 3
5 VCC
4Y
001aaf412
A2
5 n.c.
GND 3
4Y
001aaf413
Transparent top view
Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886
(TSSOP5)
(XSON6)
6.2 Pin description
Table 3.
Symbol
n.c.
A
GND
Y
n.c.
VCC
Pin description
Pin
TSSOP5
1
2
3
4
-
5
XSON6
1
2
3
4
5
6
7. Functional description
Description
not connected
data input
ground (0 V)
data output
not connected
supply voltage
Table 4.
Input
A
L
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF state.
Output
Y
L
Z
74AUP1G07
n.c. 1
A2
6 VCC
5 n.c.
GND 3
4Y
001aaf414
Transparent top view
Fig 6. Pin configuration SOT891
(XSON6)
74AUP1G07_2
Product data sheet
Rev. 02 — 14 June 2007
© NXP B.V. 2007. All rights reserved.
3 of 16



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